Data storage apparatus and internal voltage trimming circuit and method for trimming an internal voltage

1. A data storage apparatus comprising:

storage; and

a controller configured to control the storage in response to a request from a host,

wherein the controller comprises an internal voltage trimming circuit, and

wherein the internal voltage trimming circuit comprises:

an integration circuit configured to generate an integration signal by integrating a difference between a test voltage output from a device under test (DUT) and a reference voltage;

a comparison circuit configured to generate a comparison signal by comparing the integration signal and the reference voltage;

a transition detection circuit configured to output a detection signal in response to level transition of the comparison signal;

a counter configured to receive an initial trimming code and generate a preliminary trimming code by increasing or reducing the initial trimming code in response to the detection signal; and

an average circuit configured to generate a final trimming code by averaging the preliminary trimming code for a determined time interval and provide the final trimming code to the storage.

2. The data storage apparatus of claim 1 , wherein the integration circuit comprises an offset cancellation unit configured to sample the difference between the test voltage and the reference voltage and generate the integration signal by integrating a sampling signal, wherein the offset cancellation unit is further configured to remove an offset from the sampling signal.

3. The data storage apparatus of claim 2 , wherein the integration circuit further comprises a pole addition unit configured to allow an output level of the integration signal to converge to a level of the reference voltage during the sampling of the difference between the test voltage and the reference voltage.

4. The data storage apparatus of claim 2 , wherein the integration circuit further comprises a zero addition unit configured to allow an output level of the integration signal to converge to a level of the reference voltage during the sampling of the difference between the test voltage and the reference voltage.

5. The data storage apparatus of claim 2 , wherein the integration circuit comprises:

a first sampling unit configured to receive a first input signal generated from the test voltage and sample a difference between the first input signal and the reference voltage in response to a first control signal and a second control signal having phases such that high level intervals are alternately repeated and non-overlapping;

a first offset cancellation unit coupled to an output terminal of the first sampling unit;

a second sampling unit configured to receive a second input signal which is generated from the test voltage as a differential signal of the first input signal and sample a difference between the second input signal and the reference voltage in response to the first control signal and the second control signal;

a second offset cancellation unit coupled to an output terminal of the second sampling unit, wherein the offset cancellation unit comprises the first and second offset cancellation unit;

an amplification unit configured to output a first integration signal by receiving and amplifying an output signal of the first offset cancellation unit and output a second integration signal by receiving and amplifying an output signal of the second offset cancellation unit;

a first integration unit coupled between the output terminal of the first sampling unit and an output terminal of the first integration signal; and

a second integration unit coupled between the output terminal of the second sampling unit and an output terminal of the second integration signal.

6. The data storage apparatus of claim 5 , wherein the integration unit further comprises:

a first pole addition unit coupled between the output terminal of the first sampling unit and the output terminal of the first integration signal; and

a second pole addition unit coupled between the output terminal of the second sampling unit and the output terminal of the second integration signal.

7. The data storage apparatus of claim 5 , wherein the integration unit further comprises:

a first zero addition unit coupled between an input terminal of the first sampling unit and the first integration unit; and

a second zero addition unit coupled between an input terminal of the second sampling unit and the second integration unit.

8. An internal voltage trimming circuit configured to provide a trimming code for generating an internal voltage of a semiconductor device, wherein the internal voltage trimming circuit comprises:

an integration circuit configured to generate an integration signal by integrating a difference between a test voltage output from a device under test (DUT) and a reference voltage;

a comparison circuit configured to generate a comparison signal by comparing the integration signal and the reference voltage;

a transition detection circuit configured to output a detection signal in response to level transition of the comparison signal;

a counter configured to receive an initial trimming code and generate a preliminary trimming code by increasing or reducing the initial trimming code in response to the detection signal; and

an average circuit configured to generate a final trimming code by averaging the preliminary trimming code for a determined time interval and provide the final trimming code to the semiconductor device.

9. The internal voltage trimming circuit of claim 8 , wherein the integration circuit comprises an offset cancellation unit configured to sample the difference between the test voltage and the reference voltage and generate the integration signal by integrating a sampling signal, wherein the offset cancellation unit is further configured to remove an offset from the sampling signal.

10. The internal voltage trimming circuit of claim 9 , wherein the integration circuit further comprises a pole addition unit configured to allow an output level of the integration signal to converge to a level of the reference voltage during the sampling of the difference between the test voltage and the reference voltage.

11. The internal voltage trimming circuit of claim 9 , wherein the integration circuit further comprises a zero addition unit configured to allow an output level of the integration signal to converge to a level of the reference voltage during the sampling of the difference.

12. The internal voltage trimming circuit of claim 9 , wherein the semiconductor device is a storage apparatus configured to input and output data according to control of a controller, and wherein the internal voltage trimming circuit is embedded in the controller as a built-in self-test (BIST) device.

13. A trimming method performed by an internal voltage trimming to circuit for generating an internal voltage of a semiconductor device, the method comprising:

generating an integration signal by integrating a difference between a test voltage output from a device under test (DUT) and a reference voltage;

generating a comparison signal by comparing the integration signal and the reference voltage;

outputting a detection signal in response to level transition of the comparison signal;

generating a preliminary trimming code by increasing or reducing an initial trimming code in response to the detection signal; and

generating a final trimming code by averaging the preliminary trimming code for a determined time interval and providing the final trimming code to the semiconductor device.

14. The method of claim 13 , wherein integrating a difference between a test voltage output from a DUT and a reference voltage comprises:

sampling the difference between the test voltage and the reference voltage; and

removing an offset from a sampling signal; and

generating the integration signal by integrating the offset-removed sampling signal.

15. The method of claim 14 , wherein integrating a difference between a test voltage output from a DUT and a reference voltage further comprises allowing an output level of the integration signal to converge to a level of the reference level during the sampling of the difference.