Neural network computation circuit including semiconductor storage elements

1. A neural network computation circuit including semiconductor storage elements, the neural network computation circuit comprising:

a memory array that includes a plurality of memory cells arranged in rows and columns, each of the plurality of memory cells being connected to one of a plurality of word lines and one of a plurality of bit lines;

a multiple-word line selection circuit that sets one or more word lines of the plurality of word lines in a selected state or a non-selected state;

n determination circuits that perform computation operations of neurons of a neural network, n being an integer of 1 or more;

a column selection circuit that connects one or more of the plurality of bit lines to each of the n determination circuits; and

a control circuit that controls the multiple-word line selection circuit,

wherein the plurality of word lines are logically divided into a plurality of word line areas, each of the plurality of word line areas including n word lines,

the multiple-word line selection circuit includes a plurality of in-area multiple-word line selection circuits that are provided in one-to-one correspondence to the plurality of word line areas, each of the plurality of in-area multiple-word line selection circuits setting the n word lines included in a corresponding one of the plurality of word line areas in a selected state or a non-selected state,

each of the plurality of in-area multiple-word line selection circuits includes a first latch and a second latch provided for each of the n word lines, determines a set state of the first latch and a set state of the second latch based on an area selection signal, an in-area word line control signal, a first latch control signal, a second latch control signal, and a word line selection signal that are controlled by the control circuit, and sets a corresponding one of the n word lines in a selected state or a non-selected state based on the set state of the first latch, and

in a multiple-word line selected state selected by the multiple-word line selection circuit, the n determination circuits each perform a determining operation of outputting a first logical value or a second logical value as output data of the computation operations of the neurons of the neural network based on a voltage state of the one or more of the plurality of bit lines connected by the column selection circuit or a current state of electric current flowing through the one or more of the plurality of bit lines.

2. The neural network computation circuit according to claim 1 ,

wherein the control circuit performs the determining operation a plurality of times in the multiple-word line selected state,

the control circuit sequentially performs an operation of determining, based on n results obtained in a single instance of the determining operation, set states of n second latches provided in one of the plurality of in-area multiple-word line selection circuits selected based on the area selection signal, while switching the area selection signal, the n second latches being the second latch provided for each of the n word lines, and

after performing the determining operation the plurality of times, the control circuit transfers and sets the set states of the n second latches to and in first latches connected to the n second latches, the first latches being the first latch provided for each of the n word lines.

3. The neural network computation circuit according to claim 1 ,

wherein the multiple-word line selected state corresponds to input data of the neurons of the neural network.

4. The neural network computation circuit according to claim 1 ,

wherein each of the plurality of memory cells stores connection weighting factors of the neural network.

5. The neural network computation circuit according to claim 1 ,

wherein each of the plurality of memory cells is a resistance variable non-volatile memory element that is formed using a resistance variable element, and stores connection weighting factors of the neural network as resistance values.

6. A neural network computation circuit including semiconductor storage elements, the neural network computation circuit comprising:

a memory array that includes a plurality of memory cells arranged in rows and columns, each of the plurality of memory cells being connected to one of a plurality of word lines and one of a plurality of bit lines;

a multiple-word line selection circuit that sets one or more word lines of the plurality of word lines in a selected state or a non-selected state;

n determination circuits that perform computation operations of neurons of a neural network, n being an integer of 1 or more;

one or more readout circuits that determine logic states of the plurality of memory cells;

a column selection circuit that connects one or more of the plurality of bit lines to each of the n determination circuits or to the one or more readout circuits; and

a control circuit that controls the multiple-word line selection circuit,

wherein the plurality of word lines are logically divided into a plurality of word line areas, each of the plurality of word line areas including n word lines,

the multiple-word line selection circuit includes a plurality of in-area multiple-word line selection circuits that are provided in one-to-one correspondence to the plurality of word line areas, each of the plurality of in-area multiple-word line selection circuits being capable of performing two operations: an operation in a neural network computation operation mode of setting the n word lines included in a corresponding one of the plurality of word line areas in a selected state or a non-selected state; and an operation in a memory operation mode of setting one word line included in the corresponding one of the plurality of word line areas in a selected state or a non-selected state by switching between the two operations,

each of the plurality of in-area multiple-word line selection circuits includes a first latch, a second latch, and a switching circuit that is connected to an output of the first latch provided for each of the n word lines,

with an area selection signal, an in-area word line control signal, a first latch control signal, a second latch control signal, a word line selection signal, and a mode switching signal that are controlled by the control circuit, when the mode switching signal is in a signal state that corresponds to the neural network computation operation mode, each of the plurality of in-area multiple-word line selection circuits determines a set state of the first latch and a set state of the second latch and sets the corresponding word line based on the set state of the first latch via the switching circuit in a selected state or a non-selected state, as the neural network computation operation mode, and

when the mode switching signal is in a signal state that corresponds to the memory operation mode, each of the plurality of in-area multiple-word line selection circuits sets the corresponding word line based on the area selection signal, the in-area word line control signal, and the word line selection signal via the switching circuit in a selected state or a non-selected state, as the memory operation mode,

during the neural network computation operation mode, in a multiple-word line selected state selected by the multiple-word line selection circuit, the n determination circuits each perform a determining operation of outputting a first logical value or a second logical value as output data of the computation operations of the neurons of the neural network based on a voltage state of the one or more of the plurality of bit lines connected by the column selection circuit or a current state of electric current flowing through the one or more of the plurality of bit lines,

in the memory operation mode, in a state in which one word line is selected by the multiple-word line selection circuit, the one or more readout circuits performs a readout/determining operation of outputting a first logical value or a second logical value as memory data based on a voltage state of the one or more of the plurality of bit lines connected by the column selection circuit or a current state of electric current flowing through the one or more of the plurality of bit lines.

7. The neural network computation circuit according to claim 6 ,

wherein the control circuit performs the determining operation a plurality of times in the multiple-word line selected state,

the control circuit sequentially performs an operation of determining, based on n results obtained in a single instance of the determining operation, set states of n second latches provided in one of the plurality of in-area multiple-word line selection circuits selected based on the area selection signal, while switching the area selection signal, the n second latches being the second latch provided for each of the n word lines, and

after performing the determining operation the plurality of times, the control circuit transfers and sets the set states of the n second latches to and in first latches connected to the n second latches, the first latches being the first latch provided for each of the n word lines.

8. The neural network computation circuit according to claim 6 ,

wherein the multiple-word line selected state during the neural network computation operation mode corresponds to input data of the neurons of the neural network.

9. The neural network computation circuit according to claim 6 ,

wherein each of the plurality of memory cells stores connection weighting factors of the neural network or memory data.

10. The neural network computation circuit according to claim 6 ,

wherein each of the plurality of memory cells is a resistance variable non-volatile memory element that is formed using a resistance variable element, and stores connection weighting factors of the neural network as resistance values or stores memory data.