Startup detection for parallel power converters
Circuits and methods for controlling the startup of multiple parallel power converters that avoid in-rush current and/or switch over-stress in an added power converter or a power converter having one or more fault conditions. Embodiments include node status detectors coupled to selected nodes within parallel-connected power converters to monitor voltage and/or current, and configured in some embodiments to work in parallel with an output status detector measuring the output voltage of an associated power converter during startup. With charge pump-based power converters, the node status detectors ensure that the pump capacitors of each power converter are adequately charged while the output capacitor is charged as well. For such embodiments, a soft-start period of startup may be considered finished if both the shared output capacitors and the pump capacitors of each power converter are charged to selected target values. Embodiments may also be used for fault detection during steady-state operation.
1. A detection circuit configured to be coupled to a plurality of parallel power converters having direct-connected outputs, including, for at least one power converter:
(a) at least one node status detector each coupled to a corresponding node within the at least one power converter and configured to generate a corresponding node flag signal if the voltage and/or current at the corresponding node has a selected node value;
(b) an output status detector coupled to the output of the at least one power converter and configured to generate an output flag signal if a voltage at the output has a selected output value; and
(c) a status validation circuit configured to receive the output flag signal from the output status detector and the corresponding node flag signal from the at least one node status detector, and generate a logic signal if all of the received flag signals have been asserted.
2. The invention of claim 1 , wherein the at least one power converter is configured to transition to a steady-state mode of operation in response to receipt of at least the logic signal from the status validation circuit.
3. The invention of claim 1 , wherein the at least one power converter is prevented from transitioning to a steady-state mode of operation in the absence of receipt of the logic signal from the status validation circuit.
4. The invention of claim 1 , wherein the at least one power converter is configured to transition out of a steady-state mode of operation in response to receipt of at least the logic signal from the status validation circuit.
5. The invention of claim 1 , wherein the at least one power converter includes a switched-capacitor power converter.
6. The invention of claim 1 , wherein the at least one power converter includes a symmetric cascade multiplier charge pump.
7. The invention of claim 1 , wherein the at least one node status detector includes:
(a) a voltage divider network configured to receive input voltages from same-stage node pairs within the at least one power converter and output a scaled sum of the input voltages; and
(b) a comparison circuit, coupled to the output of the voltage divider network and to a reference voltage, configured to generate the corresponding node flag signal if the voltage at the corresponding node has a selected node value.
8. A detection circuit configured to be coupled to a plurality of parallel power converters having direct-connected outputs, including, for at least one power converter:
(a) at least one node status detector each coupled to a corresponding node within the at least one power converter and configured to generate a corresponding node flag signal if the voltage and/or current at the corresponding node is within a selected percentage of a corresponding target steady-state node value;
(b) an output status detector coupled to the output of the at least one power converter and configured to generate an output flag signal if the voltage at the output is within a selected percentage of a corresponding target steady-state output value; and
(c) a status validation circuit coupled to the at least one power converter, the output status detector, and the at least one node status detector, the status validation circuit configured to receive the output flag signal from the output status detector and the corresponding node flag signal from the at least one node status detector and generate a logic signal if all of the received flag signals have been asserted.
9. The invention of claim 8 , wherein the at least one power converter is configured to transition to a steady-state mode of operation in response to receipt of at least the logic signal from the status validation circuit.
10. The invention of claim 8 , wherein the at least one power converter is prevented from transitioning to a steady-state mode of operation in the absence of receipt of the logic signal from the status validation circuit.
11. The invention of claim 8 , wherein the at least one power converter is configured to transition out of a steady-state mode of operation in response to receipt of at least the logic signal from the status validation circuit.
12. The invention of claim 8 , wherein the at least one power converter includes a switched-capacitor power converter.
13. The invention of claim 8 , wherein the at least one power converter includes a symmetric cascade multiplier charge pump.
14. The invention of claim 8 , wherein the at least one node status detector includes:
(a) a voltage divider network configured to receive input voltages from same-stage node pairs within the at least one power converter and output a scaled sum of the input voltages; and
(b) a comparison circuit, coupled to the output of the voltage divider network and to a reference voltage, configured to generate the corresponding node flag signal if the voltage at the corresponding node has a selected node value.
15. A detection circuit configured to be coupled to a plurality of power converters having direct-connected outputs, including, for at least one power converter:
(a) at least one node status detector each coupled to a corresponding pump capacitor node within the at least one power converter and configured to generate a corresponding node flag signal if the corresponding pump capacitor node is adequately charged to a selected level;
(b) an output status detector coupled to an output capacitor of the at least one power converter and configured to generate an output flag signal if the output capacitor is adequately charged to a selected level; and
(c) a status validation circuit coupled to the at least one power converter, the output status detector, and the at least one node status detector, the status validation circuit configured to receive the output flag signal from the output status detector and the corresponding node flag signal from the at least one node status detector and provide a logic signal to the at least one power converter if all of the received flag signals have been asserted;
wherein the at least one power converter is configured to transition to a steady-state mode of operation in response to receipt of at least the logic signal from the status validation circuit.
16. The invention of claim 15 , wherein the at least one power converter includes a charge pump.
17. The invention of claim 15 , wherein the at least one power converter includes a symmetric cascade multiplier charge pump.
18. The invention of claim 15 , wherein the at least one node status detector includes:
(a) a voltage divider network configured to receive input voltages from same-stage pump capacitor node pairs and output a scaled sum of the input voltages; and
(b) a comparison circuit, coupled to the output of the voltage divider network and to a reference voltage, configured to generate the corresponding node flag signal if the voltages of the same-stage pump capacitor node pairs have selected values.