Semiconductor device
A semiconductor device includes a semiconductor substrate: a vertical Hall element formed in the semiconductor substrate, and having a magnetosensitive portion; a first excitation wiring disposed above the magnetosensitive portion, and configured to apply a first calibration magnetic field (M 1 ) to the magnetosensitive portion; and second excitation wirings disposed above the magnetosensitive portion on one side and on another side of the first excitation wiring, respectively, along the first excitation wiring as viewed in plan view from immediately above a front surface of the semiconductor substrate, and configured to apply second calibration magnetic fields (M 2 ) to the magnetosensitive portion.
1. A semiconductor device, comprising:
a semiconductor substrate;
a vertical Hall element formed in the semiconductor substrate, and having a magneto sensitive portion;
a first excitation wiring disposed above the magnetosensitive portion, wherein a center position in a width direction of the first excitation wiring matches a center position in the width direction of the magnetosensitive portion, and wherein the first excitation wiring is configured to apply a first magnetic field to the magnetosensitive portion;
a second excitation wiring disposed above the magnetosensitive portion on a first side of the first excitation wiring along the first excitation wiring as viewed in plan view from immediately above a front surface of the semiconductor substrate, and configured to apply a second magnetic field to the magneto sensitive portion;
a third excitation wiring disposed above the magnetosensitive portion on a second side of the first excitation wiring along the first excitation wiring as viewed in plan view from immediately above the front surface of the semiconductor substrate wherein the second side is opposite the first side, and wherein the third excitation wiring is configured to apply a third magnetic field to the magnetosensitive portion; and
wherein the second excitation wiring and the third excitation wiring are disposed symmetrically with respect to the first excitation wiring as viewed in the plan view.
2. The semiconductor device according to claim 1 , wherein the second excitation wiring and the third excitation wiring are disposed outside of the magneto sensitive portion as viewed in the plan view.
3. The semiconductor device according to claim 1 , wherein the first excitation wiring is disposed higher than the second excitation wiring and the third excitation wiring with respect to the magnetosensitive portion.
4. The semiconductor device according to claim 1 , wherein the first excitation wiring is electrically connected in series to the second excitation wiring and the third excitation wiring.
5. The semiconductor device according to claim 1 ,
wherein the first excitation wiring comprises a plurality of first wiring portions disposed in parallel to one another, the plurality of first wiring portions being electrically connected in series to one another.
6. The semiconductor device according to claim 1 ,
wherein the second excitation wiring comprises a plurality of second wiring portions disposed in parallel to one another, the plurality of second wiring portions being electrically connected in series to one another; and
wherein the third excitation wiring comprises a plurality of third wiring portions disposed in parallel to one another, the plurality of third wiring portions being electrically connected in series to one another.
7. The semiconductor device according to claim 2 , wherein the second excitation wiring and the third excitation wiring are disposed symmetrically with respect to the first excitation wiring as viewed in the plan view.
8. The semiconductor device according to claim 1 , wherein the first excitation wiring is disposed higher than the second excitation wiring and the third excitation wiring with respect to the magnetosensitive portion.
9. The semiconductor device according to claim 3 , wherein the first excitation wiring is electrically connected in series to the second excitation wiring and the third excitation wiring.
10. The semiconductor device according to claim 4 ,
wherein the first excitation wiring comprises a plurality of first wiring portions disposed in parallel to one another, the plurality of first wiring portions being electrically connected in series to one another.
11. The semiconductor device according to claim 5 ,
wherein each of the second excitation wiring comprises a plurality of second wiring portions disposed in parallel to one another, the plurality of second wiring portions being electrically connected in series to one another; and
wherein the third excitation wiring comprises a plurality of third wiring portions disposed in parallel to one another, the plurality of third wiring portions being electrically connected in series to one another.