IP Library Granted Patent US 11,372,583
Granted Patent B2
US 11,372,583 · App. 16/808,259 · Granted Jun 28, 2022

Storage device and control method for maintaining control information in the event of power failure

Inventors: Sachie Tajima (Tokyo, JP); Shintaro Ito (Tokyo, JP)
Assignee: HITACHI, LTD.
G06F3/0659G06F3/0622G06F3/0685G06F12/1009G06F2212/657
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Quick Facts
Patent No.
US 11,372,583
App. No.
16/808,259
Granted
Jun 28, 2022
Kind
B2
Abstract

To appropriately access data managed before a supply of power is stopped. A storage device that receives an I/O request from a host computer and performs an I/O processing in response to the I/O request includes a CPU, a nonvolatile medium, and a memory having access performance higher than that of the nonvolatile medium. The CPU stores control information about a control for performing the I/O processing in the memory and the nonvolatile medium. The control information stored in the nonvolatile medium includes address conversion information for converting a physical address of a drive in which target data of the I/O request is stored and a logical address that indicates a logical area of data stored in the physical address.

Claims (56)

1. A storage device that receives an I/O request from a host computer and performs an I/O processing in response to the I/O request, the storage device comprising:

a processor unit;

a first nonvolatile medium; and

a memory having access performance higher than that of the first nonvolatile medium,

wherein the storage device includes control information about a control performing the I/O processing,

wherein the control information includes address conversion information for converting a physical address of a memory device in which target data of the I/O request is stored and a logical address that indicates a logical area of data stored in the physical address,

wherein the address conversion information includes physical-logical address conversion information for converting the physical address into the logical address, and logical-physical address conversion information for converting the logical address into the physical address,

wherein the processor unit:

stores the physical-logical address conversion information in the first nonvolatile medium and the memory;

stores the logical-physical address conversion information in the memory; and when returning from a power source cut off, generates the logical-physical address conversion information based on the physical-logical address conversion information in the first nonvolatile medium,

wherein the physical-logical address conversion information is managed by a one-stage table, and the logical-physical address conversion information is managed by a multi-stage table,

wherein the control information stored in the memory is further stored into a second nonvolatile medium, and a storage completion flag is stored in the second nonvolatile memory to indicate that the control information has been successfully stored in the second nonvolatile memory,

wherein the logical-physical address conversion information is read from the second nonvolatile medium when the storage completion flag is present, and

wherein the logical-physical address conversion information is created from the physical-logical address conversion information in the first nonvolatile medium when the storage completion flag is not present.

2. The storage device according to claim 1 , wherein the processor unit synchronously stores the address conversion information of the control information into the memory and the first nonvolatile medium, and

wherein the processor unit performs the I/O processing using the address conversion information stored in the memory.

3. The storage device according to claim 2 , wherein the processor unit performs:

first storage of synchronously storing the control information including the address conversion information into the memory and the first nonvolatile medium; and

second storage of storing the control information into a second nonvolatile medium at a frequency smaller than a frequency of the first storage.

4. The storage device according to claim 2 , wherein the address conversion information stored in the memory and the address conversion information synchronously stored in the first nonvolatile medium have a same target address.

5. The storage device according to claim 1 , wherein the processor unit uses the logical-physical address conversion information to access data in the memory device.

6. A storage device that receives an I/O request from a host computer and performs an I/O processing in response to the I/O request, the storage device comprising:

a processor unit;

a first nonvolatile medium; and

a memory having access performance higher than that of the first nonvolatile medium,

wherein the storage device includes control information about a control performing the I/O processing,

wherein the control information includes address conversion information for converting a physical address of a memory device in which target data of the I/O request is stored and a logical address that indicates a logical area of data stored in the physical address,

wherein the address conversion information includes physical-logical address conversion information for converting the physical address into the logical address, and logical-physical address conversion information for converting the logical address into the physical address,

wherein the processor unit:

stores the physical-logical address conversion information in the first nonvolatile medium and the memory;

stores the logical-physical address conversion information in the memory; and

when returning from a power source cut off, generates the logical-physical address conversion information based on the physical-logical address conversion information in the first nonvolatile medium,

wherein the processor unit synchronously stores the address conversion information of the control information into the memory and the first nonvolatile medium, and

wherein the processor unit performs the I/O processing using the address conversion information stored in the memory,

wherein the processor unit performs:

first storage of synchronously storing the control information including the address conversion information into the memory and the first nonvolatile medium; and

second storage of storing the control information into a second nonvolatile medium at a frequency smaller than a frequency of the first storage,

wherein the control information stored in the memory is further stored into the second nonvolatile medium by performing the second storage, and a storage completion flag is stored in the second nonvolatile memory to indicate that the control information has been successfully stored in the second nonvolatile memory,

wherein address conversion information on which the second storage is performed is read from the second nonvolatile medium when the storage completion flag is present, and

wherein address conversion information on which the first storage is performed is read from the first nonvolatile medium when the storage completion flag is not present.

7. The storage device according to claim 1 , wherein the control information stored in the memory includes a cache space, monitor information, and a part of the address conversion information.

8. The storage device according to claim 7 , wherein the control information stored in the first nonvolatile medium does not include a cache space or monitor information.

9. The storage device according to claim 1 , wherein the first nonvolatile medium is a memory device that stores data relating to the I/O processing.

10. The storage device according to claim 1 , wherein the memory is volatile.

11. A control method in a storage device that receives an I/O request from a host computer and performs an I/O processing in response to the I/O request,

the storage device including a processor unit, a first nonvolatile medium, and a memory having access performance higher than that of the first nonvolatile medium,

the control method comprising:

storing control information about a control of performing the I/O processing, the control information including address conversion information for converting a physical address of a memory device in which target data of the I/O request is stored and a logical address that indicates a logical area of data stored in the physical address, the address conversion information including physical-logical address conversion information for converting the physical address into the logical address, and logical-physical address conversion information for converting the logical address into the physical address,

the processor unit

storing the physical-logical address conversion information in the first nonvolatile medium and the memory,

storing the logical-physical address conversion information in the memory, and

when, in response to returning from a power source cut off, generating the logical-physical address conversion information based on the physical-logical address conversion information in the first nonvolatile medium,

wherein the physical-logical address conversion information is managed by a one-stage table, and the logical-physical address conversion information is managed by a multi-stage table,

wherein the control information stored in the memory is further stored into a second nonvolatile medium, and a storage completion flag is stored in the second nonvolatile memory to indicate that the control information has been successfully stored in the second nonvolatile memory,

wherein the logical-physical address conversion information is read from the second nonvolatile medium when the storage completion flag is present, and

wherein the logical-physical address conversion information is created from the physical-logical address conversion information in the first nonvolatile medium when the storage completion flag is not present.

Assignments (2)
COMPANY SPLIT Recorded Aug 20, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069518/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2020
From: TAJIMA, SACHIE; ITO, SHINTARO
To: HITACHI, LTD.
Reel/Frame 052001/0165 →
Priority Claims (1)
JP JP2019-116944 · Jun 25, 2019 · national
Continuity (1)
Related Publication 20200409604A1 · Dec 31, 2020