Hardware-based coherency checking techniques
Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.
1. A system, comprising:
a plurality of memory components; and
a processing device operatively coupled with the plurality of memory components, the processing device to:
receive a first command that indicates a first logical address of the plurality of memory components;
identify a first slot identification associated with the first logical address;
lock, responsive to the first command, a first entry of a coherency record associated with the first slot identification;
receive, after the first entry of the coherency record is locked, an indication that a write operation associated with the first entry of the coherency record is complete; and
release, responsive to the indication, the first entry of the coherency record.
2. The system of claim 1 , wherein:
the processing device comprises a coherency block that receives the first command and the indication, a slot buffer coupled with the coherency block that provides the indication, and the coherency record, and wherein the processing device is further to:
receive, after the first entry of the coherency record is locked and prior to the release of the first entry of the coherency record, a second command at the coherency block that indicates a coherency check associated with the first slot identification; and
output, from the coherency block, an indication that the first slot identification is locked and the first logical address.
3. The system of claim 2 , wherein:
the indication that the first slot identification is locked and the first logical address is provided to a status queue of the coherency block that is located in a level-zero cache coupled with the coherency block and a central processing unit (CPU) of the processing device.
4. The system of claim 1 , further comprising:
the processing device further to:
receive, after the first entry of the coherency record is released, a second command that indicates a coherency check associated with the first slot identification; and
output an indication of a coherency miss for the first slot identification, and wherein the coherency miss indicates that data stored at the plurality of memory components is available to be provided responsive to the second command.
5. The system of claim 4 , wherein:
the indication that the first slot identification is locked and the first logical address is provided to a status queue of a coherency block that is located in a level-zero cache coupled with a central processing unit (CPU) of the processing device.
6. The system of claim 1 , wherein:
the first command is received in a command queue and is associated with a write command of the plurality of memory components.
7. The system of claim 6 , wherein:
the command queue is located in a level-zero cache that is coupled with a central processing unit (CPU) of the processing device, and wherein the CPU writes the first command to the command queue asynchronously relative to command transmissions via a system bus that is coupled with the CPU.
8. The system of claim 1 , wherein:
the first slot identification is a buffer slot index provided by a slot index block of the processing device.
9. The system of claim 8 , wherein:
the first logical address is a provided by a logical address allocation block of the processing device, and the coherency record is maintained in a logical address record storage block of the processing device.
10. A system, comprising:
a plurality of memory components; and
a processing device operatively coupled with the plurality of memory components, the processing device to:
receive a coherency check command that indicates a first slot identification of the plurality of memory components;
determine that one or more logical addresses associated with the first slot identification are locked at a coherency record; and
output an indication that the first slot identification is locked and the one or more logical addresses associated with the first slot identification.
11. The system of claim 10 , further comprising:
the processing device further to:
identify, at a logical address allocation block of the processing device, the one or more logical addresses associated with the first slot identification.
12. The system of claim 11 , wherein:
the indication that the first slot identification is locked and the one or more logical addresses associated are provided to a status queue that is located in a level-zero cache coupled with a central processing unit (CPU) of the processing device.
13. The system of claim 10 , further comprising:
the processing device further to:
receive a subsequent coherency check command that indicates a second slot identification of the plurality of memory components;
determine that one or more logical addresses associated with the second slot identification are unlocked at the coherency record; and
output an indication of a coherency miss for the second slot identification.
14. The system of claim 13 , wherein:
the indication that the first slot identification is locked and the one or more logical addresses is provided to a status queue that is located in a level-zero cache coupled with a central processing unit (CPU) of the processing device.
15. The system of claim 10 , wherein:
the coherency check command is received in a command queue of a coherency block and is associated with a read command of the plurality of memory components, and wherein the command queue is located in a level-zero cache coupled with the coherency block and a central processing unit (CPU) of the processing device.
16. A method, comprising:
receiving a first command that indicates a first logical address of a plurality of memory components coupled with a memory sub-system controller;
identifying a first slot identification associated with the first logical address;
locking, responsive to the first command, a first entry of a coherency record associated with the first slot identification;
receiving, after the first entry of the coherency record is locked, an indication that a write operation associated with the first entry of the coherency record is complete; and
releasing, responsive to the indication, the first entry of the coherency record.
17. The method of claim 16 , further comprising:
receiving, after the first entry of the coherency record is locked and prior to the releasing of the first entry of the coherency record, a second command that indicates a coherency check associated with the first slot identification; and
outputting an indication that the first slot identification is locked and the first logical address.
18. The method of claim 16 , further comprising:
receiving, after the first entry of the coherency record is released, a second command that indicates a coherency check associated with the first slot identification; and
outputting an indication of a coherency miss for the first slot identification.
19. The method of claim 16 , wherein:
the first command is received in a command queue of a coherency block and is associated with a write command of the plurality of memory components.
20. The method of claim 19 , wherein:
the command queue is located in a level-zero cache that is coupled with the coherency block and a central processing unit (CPU) of a processing device, and wherein the CPU writes the first command to the command queue asynchronously relative to command transmissions via a system bus that is coupled with the CPU.