IP Library Granted Patent US 11,226,770
Granted Patent B2
US 11,226,770 · App. 16/812,719 · Granted Jan 18, 2022

Memory protocol

Inventors: Robert M. Walker (Raleigh, NC); Frank F. Ross (Boise, ID)
Assignee: Micron Technology, Inc.
G06F3/0659G06F3/061G06F3/0656G06F3/0679G06F13/16G06F13/4234
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,226,770
App. No.
16/812,719
Granted
Jan 18, 2022
Kind
B2
Abstract

The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (RID) number to the first chunk of data and a second RID number to the second chunk of data, sending the first chunk of data and the first RID number to a host, and sending the second chunk of data and the second RID number to the host. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.

Claims (29)

1. An apparatus, comprising: a memory device; and

circuitry coupled to the memory device configured to:

receive a read command that includes an indication of a quantity of data to be transferred and an indication that a portion of data associated with the command is critical, wherein the read command is sent without regard to timing parameters and wherein the quantity of data to be transferred is different than a quantity of data transferred by another read command;

execute the read command by sending a read ready signal to indicate the portion of data associated with the read command is ready based on the indication that the portion of data is critical in response to receiving the read command and sending data associated with the read command and a data packet that includes a read identification (RID) number in response to receiving a send command.

2. The apparatus of claim 1 , wherein the circuitry is configured to execute the read command by sending a read ready signal in response to receiving the read command.

3. The apparatus of claim 2 , wherein the read ready signal indicates the data associated with the command is ready to send.

4. The apparatus of claim 1 , wherein the circuitry is configured to execute the read command by sending the data associated with the command and the data packet in response to receiving a send command.

5. The apparatus of claim 1 , wherein the data packet include write credit information.

6. The apparatus of claim 1 , wherein the data packet includes ECC information.

7. The apparatus of claim 1 , wherein the data packet includes block identification information to indicate a number of chunks of data included in the data associated with the command.

8. An apparatus, comprising: a memory device; and

circuitry coupled to the memory device configured to:

receive a read command that includes an indication of a quantity of data to be transferred and an indication of an order in which to return a plurality of portions of data associated with the read command, wherein the read command is sent without regard to timing parameters and wherein the quantity of data to be transferred is different than a quantity of data transferred by another read command;

send a read ready command to indicate a first portion of the plurality of portions of data associated with the read command is ready to send based the indication of the order in which to return the plurality of portions of data; and

send the first portion of data associated with the command and a data packet to the host.

9. The apparatus of claim 8 , wherein the data packet includes a 10 bit read identification (RID) number.

10. The apparatus of claim 9 , wherein the read command includes the RID number.

11. The apparatus of claim 8 , wherein the circuitry is configured to receive a send command to indicate a host is ready to receive the data associated with the read command.

12. The apparatus of claim 8 , wherein the data packet includes write credit information.

13. The apparatus of claim 8 , wherein the data packet includes ECC information.

14. The apparatus of claim 8 , wherein the data packet includes block identification information to indicate a number of chunks of data included in the data associated with the command.

15. A method, comprising:

sending a read ready command in response to receive a read command requesting data, wherein the read ready command indicates a first portion of data associated with the read command is ready to send based an indication in the read command that the first portion of data is critical, wherein the read command includes an indication of a quantity of data to be transferred, wherein the read command is sent without regard to timing parameters, and wherein the quantity of data to be transferred is different than a quantity of data transferred by another read command; and

sending the first portion of data associated with the read command and a data packet in response to receiving an indication that a host is ready to receive the data associated with the read command.

16. The method of claim 15 , wherein sending the data packet includes sending a 10 bit read identification (RID) number.

17. The method of claim 15 , further including sending the read ready command to indicate a memory device has the data associated with the read command ready to send.

18. The method of claim 15 , further including receiving a send command to indicate the host is ready to receive the data associated with the read command.

19. The method of claim 15 , wherein sending the data packet includes sending write credit information.

20. The method of claim 15 , wherein sending the data packet includes sending ECC information.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2024
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 067230/0485 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2020
From: WALKER, ROBERT M.; ROSS, FRANK F.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 052053/0013 →
Continuity (2)
Continuation 15366504 · Dec 1, 2016
Related Publication 20200210111A1 · Jul 2, 2020