IP Library Granted Patent US 11,347,395
Granted Patent B2
US 11,347,395 · App. 16/813,114 · Granted May 31, 2022

Cache management system and method

Inventors: Amnon Izhar (Brookline, MA); Patrick J. Weiler (Northborough, MA)
Assignee: EMC IP HOLDING COMPANY, LLC
G06F3/061G06F3/0652G06F3/0685G06F12/0866G06F2212/217
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Quick Facts
Patent No.
US 11,347,395
App. No.
16/813,114
Granted
May 31, 2022
Kind
B2
Abstract

A method, computer program product, and computing system for receiving a plurality of data streams on an SSD cache memory system associated with a backend storage system and writing a first of the plurality of data streams to a first portion of the SSD cache memory system.

Claims (32)

1. A computer-implemented method, executed on a computing device, comprising:

receiving a plurality of data streams associated with a plurality of users on an SSD cache memory system associated with a backend storage system;

writing a first of the plurality of data streams associated with a first user to a first portion of the SSD cache memory system, wherein the first portion of the SSD cache memory system includes a first erase block within the SSD cache memory system, wherein the first of the plurality of data streams associated with the first user to the first portion of the SSD cache memory system is collectively destaged into the backend storage system, wherein writing the first of the plurality of data streams includes padding the writing of the first of the plurality of data streams to fill the at least one cache page of the first group of cache pages relative to the first erase block;

writing a second of the plurality of data streams associated with a second user to a second portion of the SSD cache memory system, wherein the second portion of the SSD cache memory system includes a second erase block within the SSD cache memory system, wherein the second of the plurality of data streams associated with the second user to the second portion of the SSD cache memory system is collectively destaged into the backend storage system, wherein writing the second of the plurality of data streams includes padding the writing of the second of the plurality of data streams to fill at least one cache page of a second group of cache pages relative to the second erase block, and wherein no portion of the data comprising the second portion of the SSD cache memory system is a part of the first portion of the SSD cache memory system;

erasing the first portion of the SSD cache memory system; and

prior to erasing the first portion of the SSD cache memory system, relocating any currently-utilized data within the first portion of the SSD cache memory system to another portion of the SSD cache memory system, such that at least one cache page of a first group of cache pages relative to the first erase block within the SSD cache memory system is copied to an additional erase block associated with the another portion of the SSD memory system prior to erasing the first portion of the SSD cache memory system.

2. The computer-implemented method of claim 1 further comprising:

prior to erasing the first portion of the SSD cache memory system, writing any uncommitted data within the first portion of the SSD cache memory system to the backend storage system.

3. The computer-implemented method of claim 1 wherein writing the second of the plurality of data streams associated with the second user to the second portion of the SSD cache memory system is completed at an independent rate and a different time from writing the first of the plurality of data streams associated with the first user to the first portion of the SSD cache memory system.

4. The computer-implemented method of claim 1 wherein after the first erase block is filled with the first group of cache pages, writing the first of the plurality of data streams includes writing the first of the plurality of data streams into a first new erase block.

5. The computer-implemented method of claim 1 wherein after the second erase block is filled with the second group of cache pages, writing the second of the plurality of data streams includes writing the second of the plurality of data streams into a second new erase block.

6. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:

receiving a plurality of data streams associated with a plurality of users on an SSD cache memory system associated with a backend storage system;

writing a first of the plurality of data streams associated with a first user to a first portion of the SSD cache memory system, wherein the first portion of the SSD cache memory system includes a first erase block within the SSD cache memory system, wherein the first of the plurality of data streams associated with the first user to the first portion of the SSD cache memory system is collectively destaged into the backend storage system, wherein writing the first of the plurality of data streams includes padding the writing of the first of the plurality of data streams to fill the at least one cache page of the first group of cache pages relative to the first erase block;

writing a second of the plurality of data streams associated with a second user to a second portion of the SSD cache memory system, wherein the second portion of the SSD cache memory system includes a second erase block within the SSD cache memory system, wherein the second of the plurality of data streams associated with the second user to the second portion of the SSD cache memory system is collectively destaged into the backend storage system, wherein writing the second of the plurality of data streams includes padding the writing of the second of the plurality of data streams to fill at least one cache page of a second group of cache pages relative to the second erase block, and wherein no portion of the data comprising the second portion of the SSD cache memory system is a part of the first portion of the SSD cache memory system;

erasing the first portion of the SSD cache memory system;

prior to erasing the first portion of the SSD cache memory system, relocating any currently-utilized data within the first portion of the SSD cache memory system to another portion of the SSD cache memory system, such that at least one cache page of a first group of cache pages relative to the first erase block within the SSD cache memory system is copied to an additional erase block associated with the another portion of the SSD memory system prior to erasing the first portion of the SSD cache memory system.

7. The computer program product of claim 6 further comprising:

prior to erasing the first portion of the SSD cache memory system, writing any uncommitted data within the first portion of the SSD cache memory system to the backend storage system.

8. The computer program product of claim 6 wherein writing the second of the plurality of data streams associated with the second user to the second portion of the SSD cache memory system is completed at an independent rate and a different time from writing the first of the plurality of data streams associated with the first user to the first portion of the SSD cache memory system.

9. The computer program product of claim 6 wherein after the first erase block is filled with the first group of cache pages, writing the first of the plurality of data streams includes writing the first of the plurality of data streams into a first new erase block.

10. The computer program product of claim 6 wherein after the second erase block is filled with the second group of cache pages, writing the second of the plurality of data streams includes writing the second of the plurality of data streams into a second new erase block.

11. A computing system including a processor and memory configured to perform operations comprising:

receiving a plurality of data streams associated with a plurality of users on an SSD cache memory system associated with a backend storage system;

writing a first of the plurality of data streams associated with a first user to a first portion of the SSD cache memory system, wherein the first portion of the SSD cache memory system includes a first erase block within the SSD cache memory system, wherein the first of the plurality of data streams associated with the first user to the first portion of the SSD cache memory system is collectively destaged into the backend storage system, wherein writing the first of the plurality of data streams includes padding the writing of the first of the plurality of data streams to fill the at least one cache page of the first group of cache pages relative to the first erase block;

writing a second of the plurality of data streams associated with a second user to a second portion of the SSD cache memory system, wherein the second portion of the SSD cache memory system includes a second erase block within the SSD cache memory system, wherein the second of the plurality of data streams associated with the second user to the second portion of the SSD cache memory system is collectively destaged into the backend storage system, wherein writing the second of the plurality of data streams includes padding the writing of the second of the plurality of data streams to fill at least one cache page of a second group of cache pages relative to the second erase block, and wherein no portion of the data comprising the second portion of the SSD cache memory system is a part of the first portion of the SSD cache memory system;

erasing the first portion of the SSD cache memory system; and

prior to erasing the first portion of the SSD cache memory system, relocating any currently-utilized data within the first portion of the SSD cache memory system to another portion of the SSD cache memory system, such that at least one cache page of a first group of cache pages relative to the first erase block within the SSD cache memory system is copied to an additional erase block associated with the another portion of the SSD memory system prior to erasing the first portion of the SSD cache memory system.

12. The computing system of claim 11 further configured to perform operations comprising:

prior to erasing the first portion of the SSD cache memory system, writing any uncommitted data within the first portion of the SSD cache memory system to the backend storage system.

13. The computing system of claim 11 wherein after the first erase block is filled with the first group of cache pages, writing the first of the plurality of data streams includes writing the first of the plurality of data streams into a first new erase block.

14. The computing system of claim 11 wherein after the second erase block is filled with the second group of cache pages, writing the second of the plurality of data streams includes writing the second of the plurality of data streams into a second new erase block.

Assignments (13)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0917) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0509 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052852/0022) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0582 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0081) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0441 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052771 FRAME 0906 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0298 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052852/0022 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0081 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0917 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded May 28, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052771/0906 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2020
From: IZHAR, AMNON; WEILER, PATRICK J.
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 052056/0445 →
Continuity (2)
Continuation 15365320 · Nov 30, 2016
Related Publication 20200210068A1 · Jul 2, 2020