High connectivity device stacking
The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.
1. A device spacer disposed between two semiconductor devices, the device spacer comprising:
a frame having a first surface opposite a second surface and a lateral dimension less than a lateral dimension of each of the two semiconductor devices, the frame further comprising:
a frame material that comprises a polymer-based dielectric material having spherical ceramic fillers; and
a via comprising a via surface that defines an opening extending through the frame from the first surface to the second surface, the via having a diameter between about 10 μm and about 150 μm;
an electrical interconnection disposed within the via, the electrical interconnection disposed on the via surface; and
a barrier layer lining the via surface and disposed between the via surface and the electrical interconnection, the barrier layer comprising molybdenum.
2. The device spacer of claim 1 , wherein the ceramic fillers comprise silica particles having a maximum diameter of about 0.6 μm.
3. The device spacer of claim 2 , wherein a packing density of the silica particles is between about 0.5 and about 0.95.
4. The device spacer of claim 1 , wherein the frame has a thickness between about 400 μm and about 1600 μm.
5. The device spacer of claim 1 , wherein the via is tapered from a first diameter to a second diameter.
6. The device spacer of claim 5 , wherein the first diameter is between about 10 μm and about 100 μm, and the second diameter is between about 10 μm and about 150 μm.
7. The device spacer of claim 1 , further comprising an array of vias defining openings extending through the frame from the first surface to the second surface.
8. The device spacer of claim 7 , wherein a pitch between each via of the array of vias is between about 150 μm and about 600 μm.
9. The device spacer of claim 1 , wherein the frame has a lateral dimension less than a lateral dimension of each of the two semiconductor devices.
10. The device spacer of claim 9 , wherein the lateral dimension is parallel to the first and second surfaces of the frame.