Output buffer circuit
An output buffer circuit is disclosed to achieve a high slew rate without increasing current consumption. The output buffer circuit includes an input circuit configured to output a first signal and a second signal in response to an input signal, and a slew rate control circuit configured to connect one of the first signal and the second signal to an output terminal to control a slew rate of an output signal based on or in response to a potential difference between the input signal and the output signal.
1. An output buffer circuit, comprising:
an input circuit configured to output a first signal and a second signal in response to an input signal; and
a slew rate control circuit configured to connect one of the first signal and the second signal to an output terminal to control a slew rate of an output signal based on or in response to a potential difference between the input signal and the output signal,
wherein the slew rate control circuit includes:
a first driver transistor having a gate connected to a first output line of the input circuit, and a source connected to a highest level power supply;
a second driver transistor having a gate connected to a second output line of the input circuit, a source connected to a lowest level power supply, and a drain connected to the drain of the first driver transistor;
a first switch transistor having a gate configured to receive an input power supply and a source connected to the first output line; and
a second switch transistor having a gate configured to receive the input power supply, a source connected to the second output line, and a drain connected to a drain of the first switch transistor.
2. The circuit of claim 1 , wherein the slew rate control circuit controls the slew rate by diode-connecting one of the first driver transistor and the second driver transistor based on or in response to the potential difference.
3. The circuit of claim 1 , wherein the slew rate control circuit is in a rising slew state when the input signal is greater than the output signal; and
the slew rate control circuit is in a falling slew state when the input signal is less than the output signal.
4. The circuit of claim 1 , wherein:
the first switch transistor is on when the potential difference is equal to or greater than a reference voltage in the rising slew state; and
the first driver transistor is configured to boost the slew rate when the first switch transistor is on and is diode-connected.
5. The circuit of claim 1 , wherein:
the second switch transistor is on when the potential difference is equal to or greater than a reference voltage in the falling slew state; and
the second driver transistor is configured to boost the slew rate when the second switch transistor is on and is diode-connected.
6. An output buffer circuit, comprising:
an input circuit configured to output a first signal and a second signal in response to an input signal;
a slew rate control circuit configured to connect one of the first signal and the second signal to an output terminal and control a slew rate of an output signal based on or in response to a potential difference between the input signal and the output signal; and
a driver control circuit configured to connect a power supply line with a compensation capacitor based on or in response to an input control signal, wherein the driver control circuit includes:
a first control circuit between the highest level power supply line and a first output line of the input circuit;
a second control circuit between the lowest level power supply line and a second output line of the input circuit;
a first compensation capacitor connected to the first control circuit and an output signal line; and
a second compensation capacitor connected to the second control circuit and the output signal line.
7. The circuit of claim 6 , wherein the driver control circuit (i) connects a highest level power supply line to a first compensation capacitor when a first control signal is active, and (ii) connects a lowest level power supply line to a second compensation capacitor when a second control signal is active.
8. The circuit of claim 6 , wherein the first control circuit connects the first compensation capacitor to the highest level power supply line when the input signal transitions and the first control signal is active.
9. The circuit of claim 6 , wherein the first control circuit includes:
a first switch connected to the input circuit and the first compensation capacitor; and
a second switch connected to the highest level power supply line and the first compensation capacitor.
10. The circuit of claim 9 , wherein the first control circuit is configured to connect the first compensation capacitor with the highest level power supply line by turning the first switch off and the second switch on when the input signal transitions and the first control signal is active.
11. The circuit of claim 9 , wherein the second control circuit is configured to connect the second compensation capacitor to the lowest level power supply line when the second control signal is active.
12. The circuit of claim 11 , wherein the second control circuit includes:
a third switch connected to the input circuit and the second compensation capacitor; and
a fourth switch connected to the lowest level power supply line and the second compensation capacitor.
13. The circuit of claim 12 , wherein the second control circuit is configured to connect the second compensation capacitor to the lowest level power supply line by turning the third switch off and the fourth switch on when the input signal transitions and the first control signal is active.
14. An output buffer circuit, comprising:
an input circuit configured to output a first signal and a second signal in response to the input signal; and
a slew rate control circuit configured to connect one of the first signal and the second signal to an output terminal and control a slew rate of an output signal based on or in response to a potential difference between the input signal and the output signal,
wherein the slew rate control circuit includes:
a first switch transistor that is on when the potential difference is equal to or greater than a reference voltage and the slew rate control circuit is in a rising slew state;
a first driver transistor configured to output the first signal when the first switch transistor is on;
a second switch transistor that is on when the potential difference is equal to or greater than the reference voltage and the slew rate control circuit is in a falling slew state; and
a second driver transistor configured to output the second signal when the second switch transistor is on,
wherein each of the first switch transistor and the second switch transistor has a body connected to an output signal line.
15. An output buffer circuit, comprising:
an input circuit configured to output a first signal and a second signal in response to an input signal;
a slew rate control circuit configured to connect one of the first signal and the second signal to an output terminal and control a slew rate of an output signal based on or in response to a potential difference between the input signal and the output signal; and
a driver control circuit configured to connect a power supply line with a compensation capacitor based on or in response to an input control signal,
wherein the driver control circuit includes:
a first control circuit between a highest level power supply line and a first output line of the input circuit;
a second control circuit between a lowest level power supply line and a second output line of the input circuit;
a first compensation capacitor connected to the first control circuit and an output signal line; and
a second compensation capacitor connected to the second control circuit and the output signal line.
16. The circuit of claim 15 , wherein the first control circuit includes:
a first switch connected to the input circuit and the first compensation capacitor; and
a second switch connected to the highest level power supply line and the first compensation capacitor, and
the second control circuit includes:
a third switch connected to the input circuit and the second compensation capacitor; and
a fourth switch connected to the lowest level power supply line and the second compensation capacitor.
17. The circuit of claim 16 , wherein when the input signal rises, a first control signal turns the first switch and the third switch off, and a second control signal turns the second switch and the fourth switch on, so that the first compensation capacitor is connected to the highest level power supply line, and the second compensation capacitor is connected to the lowest level power supply line.