Custom chip to support a CPU that lacks a DisplayPort input
In some examples, a logic device may be connected to: (i) a ThunderBolt (TBT) output of a CPU that lacks a DisplayPort (DP) input and (ii) a DP output of a GPU. The logic device may determine a presence of a video signal, e.g., either: (1) TBT video from the CPU or (2) DP video from the GPU. The logic device may re-time the video signal to create re-timed video and output the re-timed video using a USB-C port. If the logic device determines that the video signal is DP, then the logic device may select a DisplayPort Alternate Mode of the USB-C port and output the re-timed video signal using four differential pairs of the USB-C port. If the logic device determines that the video signal is TBT, then the logic device may output the re-timed video signal using two differential pairs of the USB-C port.
1. A method comprising:
determining, by a logic device, that a video signal is present, wherein the logic device is connected to:
a first type of output interface of a central processing unit that lacks a second type of input interface; and
a second type of output interface of a graphics processing unit; and
wherein the video signal comprises either:
a first type of video signal output by the central processing unit; or
a second type of video signal output by the graphics processing unit;
re-timing, by the logic device, the video signal to create a re-timed video signal; and
outputting, by the logic device, the re-timed video signal over a serial bus port;
receiving a frequency sweep from a test generator to determine a transmission capabilities of the logic device.
2. The method of claim 1 , wherein outputting, by the logic device, the re-timed video signal over the serial bus port comprises:
determining that the video signal comprises the second type of video signal that is output by the graphics processing unit;
selecting a mode for the serial bus port; and
outputting the re-timed video signal using four differential pairs of pins of the serial bus port.
3. The method of claim 2 , wherein the re-timed video signal is sent to:
a 16k display device having a resolution of 15360×8640, at 60 Hertz;
two 8k display devices, each having a resolution of 7680×4320, at 120 Hertz;
two 4k display devices, each having a resolution of 3840×2160, at 144 Hertz;
three 10k display devices, each having a resolution of 10240×4320, at 60 Hertz; or
three 4k display devices, each having a resolution of 3840×2160, at 90 Hertz.
4. The method of claim 1 , wherein outputting, by the logic device, the re-timed video signal over the serial bus port comprises:
determining that the video signal comprises the first type of video signal output by the central processing unit; and
outputting the re-timed video signal using two differential pair of pins of the serial bus port.
5. The method of claim 4 , wherein the re-timed video signal is sent to:
a display device having a resolution of 3840×2160 at 120 Hertz; or
two display devices, each having a resolution of 3840×2160, at 60 Hertz.
6. The method of claim 1 , wherein re-timing, by the logic device, the video signal to create the re-timed video signal comprises:
receiving a timing signal from an external clock; and
re-timing the video signal using the timing signal to create the re-timed video signal.
7. A computing device comprising:
a serial bus port;
a central processing unit that includes a first type of output interface but excludes a second type of input interface;
a graphics processing unit that includes a second type of output interface; and
a logic device configured to perform operations comprising:
determining that a video signal is present, wherein the video signal comprises either:
a first type of video signal output by the central processing unit; or
a second type of video signal output by the graphics processing unit;
re-timing the video signal to create a re-timed video signal; and
outputting the re-timed video signal from the serial bus port;
wherein re-timing, by the logic device, the video signal to create the re-timed video signal comprises:
receiving a timing signal from an external clock; and
re-timing the video signal using the timing signal to create the re-timed video signal.
8. The computing device of claim 7 , wherein outputting the re-timed video signal from the serial bus port comprises:
determining that the video signal comprises the second type of video signal output by the graphics processing unit;
selecting a mode for the serial bus port; and
outputting the re-timed video signal using up to four differential pairs of the serial bus port to provide up to four lanes.
9. The computing device of claim 8 , wherein the re-timed video signal is sent to:
a 16k display device having a resolution of 15360×8640, at 60 Hertz;
two 8k display devices, each having a resolution of 7680×4320, at 120 Hertz;
two 4k display devices, each having a resolution of 3840×2160, at 144 Hertz;
three 10k display devices, each having a resolution of 10240×4320, at 60 Hertz; or
three 4k display devices, each having a resolution of 3840×2160, at 90 Hertz.
10. The computing device of claim 7 , wherein outputting the re-timed video signal over the serial bus port comprises:
determining that the video signal comprises the first type of video signal output by the central processing unit; and
outputting the re-timed video signal using two differential pairs of the serial bus port.
11. The computing device of claim 10 , wherein the re-timed video signal is sent to:
a display device having a resolution of 3840×2160 at 120 Hertz; or
two display devices, each having a resolution of 3840×2160, at 60 Hertz.
12. A custom chip comprising:
a multiplexer connected to:
a first type of output interface of a central processing unit that lacks a second type of input interface; and
a second type of output interface of a graphics processing unit; and
a re-timer;
wherein the custom chip is configured to:
determine that a video signal is present, wherein the video signal comprises either:
a first type of video signal output by the central processing unit; or
a second type of video signal output by the graphics processing unit;
re-time, by the re-timer, the video signal to create a re-timed video signal; and
send the re-timed video signal to a serial bus Type C port;
receiving a frequency sweep from a test generator to determine a transmission capabilities of the logic device.
13. The custom chip of claim 12 , wherein sending the re-timed video signal to the serial bus port comprises:
determining that the video signal comprises the second type of video signal that is output by the graphics processing unit;
selecting a mode for the serial bus port; and
sending the re-timed video signal using up to four differential pairs of pins of the serial bus port.
14. The custom chip of claim 13 , wherein the re-timed video signal is sent to:
a 16k display device having a resolution of 15360×8640, at 60 Hertz;
two 8k display devices, each having a resolution of 7680×4320, at 120 Hertz;
two 4k display devices, each having a resolution of 3840×2160, at 144 Hertz;
three 10k display devices, each having a resolution of 10240×4320, at 60 Hertz; or
three 4k display devices, each having a resolution of 3840×2160, at 90 Hertz.
15. The custom chip of claim 12 , wherein sending the re-timed video signal to the serial bus port comprises:
determining that the video signal comprises the first type of video signal output by the central processing unit; and
sending the re-timed video signal using two differential pairs of pins of the serial bus port.
16. The custom chip of claim 15 , wherein the re-timed video signal is sent from the serial bus port to:
a display device having a resolution of 3840×2160 at 120 Hertz; or
two display devices, each having a resolution of 3840×2160, at 60 Hertz.
17. The custom chip of claim 12 , wherein re-timing the video signal to create the re-timed video signal comprises:
receiving a timing signal from an external clock; and
re-timing, using the re-timer, the video signal using the timing signal to create the re-timed video signal.