IP Library › Granted Patent US 11,222,687

Granted Patent B2

US 11,222,687 · App. 16/815,191 · Granted Jan 11, 2022

System and method for power plane noise reduction in a memory subsystem of an information handling system

Inventors: Stuart A. Berke (Austin, TX); Jordan Chin (Austin, TX); Ralph H. Johnson (Round Rock, TX); Shiguo Luo (Austin, TX)

Assignee: Dell Products L.P.

G11C11/4076 G06F1/324 G06F13/4291 G11C5/04 G11C5/143 G11C11/4074 H02M3/156 H03L7/0814 G06F2213/0016

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Quick Facts

Patent No.: US 11,222,687
App. No.: 16/815,191
Granted: Jan 11, 2022
Kind: B2

External Links

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Abstract

An memory subsystem of an information handling system includes a memory module and a controller. The memory module includes a Registering Clock Driver (RCD) configured to receive a clock signal. The RCD includes a delay setting and a clock delay circuit to provide a selectable delayed clock signal based upon the delay setting. The memory module further includes a power management integrated circuit (PMIC) with a plurality of switching regulators. The PMIC receives the delayed clock signal and clocks the switching regulators based upon the delayed clock signal. The controller sets the first delay setting.

Claims (62)

1. A memory subsystem of an information handling system, the memory subsystem comprising:

a first memory module including:

a first memory storage device configured to receive a clock signal;

a first Registering Clock Driver (RCD) configured to receive the clock signal, and including:

a first delay setting and a first clock delay circuit to provide a selectable first delayed clock signal based upon the first delay setting; and

a second delay setting and a second clock delay circuit to provide a selectable second delayed clock signal based upon the second delay setting;

a first power management integrated circuit (PMIC) including a first switching regulator, the first PMIC configured to receive the first delayed clock signal and to clock the first switching regulator based upon the first delayed clock signal; and

a second PMIC including a second switching regulator, the second PMIC configured to receive the second delayed clock signal and to clock the second switching regulator based upon the second delayed clock signal; and

a controller configured to set the first delay setting and the second delay setting.

2. The memory subsystem of claim 1 , wherein:

the first and second PMICs are further configured to receive a voltage input to the switching regulators; and

the controller sets the first delay setting with a different setting than the second delay setting to minimize switching transients on the voltage input.

3. The memory subsystem of claim 1 , wherein the controller is a memory controller coupled to the first RCD via a command/address bus, and the controller sets the first delay setting and the second delay setting via commands sent on the command/address bus.

4. The memory subsystem of claim 1 , wherein:

the first memory module further includes a serial presence detect (SPD) hub coupled to the RCD.

5. The memory subsystem of claim 4 , wherein the controller is a baseboard management controller coupled to the SPD hub via an I2C interface, and the controller sets the first delay setting and the second delay setting via commands sent on the I2C interface.

6. The memory subsystem of claim 1 , wherein:

the first RCD further includes:

a third delay setting and a third clock delay circuit to provide a selectable third delayed clock signal based upon the third delay setting; and

a fourth delay setting and a fourth clock delay circuit to provide a selectable fourth delayed clock signal based upon the fourth delay setting;

the first memory module further includes:

a third PMIC including a third switching regulator, the third PMIC configured to receive the third delayed clock signal and to clock the third switching regulator based upon the third delayed clock signal; and

a fourth PMIC including a fourth switching regulator, the fourth PMIC configured to receive the fourth delayed clock signal and to clock the fourth switching regulator based upon the fourth delayed clock signal; and

the controller is further configured to set the third delay setting and the fourth delay setting.

7. The memory subsystem of claim 6 , wherein the controller is configured to set the first delay setting, the second delay setting, the third delay setting, and the fourth delay setting to switch the respective first switching regulator, second switching regulator, third switching regulator, and fourth switching regulator in quadrature based upon the respective first delayed clock signal, second delayed clock signal, third delayed clock signal, and fourth delayed clock signal.

8. The memory subsystem of claim 1 , wherein the first memory module is a Dual Data Rate-5 Dual In-Line Memory Module.

9. A memory module, comprising:

a memory storage device configured to receive a clock signal;

a Registering Clock Driver (RCD) configured to receive the clock signal, the RCD including;

a first delay setting and a first clock delay circuit to provide a selectable first delayed clock signal based upon the first delay setting; and

a second delay setting and a second clock delay circuit to provide a selectable second delayed clock signal based upon the second delay setting;

10. The memory module of claim 9 , wherein the RCD includes:

a first delay setting and a first clock delay circuit, wherein the first clock delay circuit delays the first clock signal based upon the first delay setting; and

a second delay setting and a second clock delay circuit, wherein the second clock delay circuit delays the second clock signal based upon the second delay setting.

11. The memory module of claim 10 , wherein the RCD receives a first setting for the delay setting and a second setting for the second delay setting from a memory controller coupled to the RCD via a command/address bus.

12. The memory module of claim 10 , further comprising:

a serial presence detect (SPD) hub coupled to the RCD, wherein the RCD receives a first setting for the first delay setting and a second setting for the second delay setting from the SPD hub.

13. The memory module of claim 9 , wherein:

the RCD further includes:

a third delay setting and a third clock delay circuit to provide a selectable third delayed clock signal based upon the third delay setting; and

a fourth delay setting and a fourth clock delay circuit to provide a selectable fourth delayed clock signal based upon the fourth delay setting; and

the memory module further includes:

14. The memory module of claim 13 , wherein the PMIC is configured to set the first delay setting, the second delay setting, the third delay setting, and the fourth delay setting to switch the respective first switching regulator, second switching regulator, third switching regulator, and fourth switching regulator in quadrature based upon the respective first delayed clock signal, second delayed clock signal, third delayed clock signal, and fourth delayed clock signal.

15. The memory module of claim 9 , wherein the memory module is a Dual Data Rate-5 Dual In-Line Memory Module.

16. A method, comprising:

receiving, by a first memory storage device of a first memory module of a memory subsystem of an information handling system, a clock signal;

receiving, by a first Registering Clock Driver (RCD) of the first memory module, the clock signal;

delaying, by a first clock delay circuit of the first RCD, the clock signal to provide a selectable first delayed clock signal based upon a first delay setting of the first RCD;

receiving, by a first power management integrated circuit (PMIC) of the memory module, the first delayed clock signal, wherein the first PMIC includes a first switching regulator;

clocking, by the first PMIC, the first switching regulators based upon the first delayed clock signal; and

delaying, by a second clock delay circuit of the first RCD, the clock signal to provide a selectable second delayed clock signal based upon a second delay setting of the first RCD;

receiving, by a second PMIC of the memory module, the second delayed clock signal, wherein the second PMIC includes a second switching regulator;

clocking, by the second PMIC, the second switching regulators based upon the second delayed clock signal; and

setting, by a controller of the memory subsystem, the first delay setting and the second delay setting.

17. The method of claim 16 , further comprising:

receiving, by the first and second PMICs, a voltage input to the respective first switching regulator and second switching regulator; and

setting, by the controller, the first delay setting with a different setting than the second delay setting to minimize switching transients on the voltage input.

18. The method of claim 16 , wherein the first memory module is a Dual Data Rate-5 Dual In-Line Memory Module (DDR5 DIMM).

Assignments (13)

RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0081) Recorded Jun 23, 2022