Computational memory

1. A processing device comprising:

an array of processing elements, each processing element including an arithmetic logic unit to perform an operation and an output selector;

interconnections among the array of processing elements to provide direct communication among neighboring processing elements of the array of processing elements wherein:

a processing element of the array of processing elements is connected to a first neighbor processing element that is immediately adjacent the processing element, wherein a first output selector of the first neighbor processing element is connected to an input of the processing element; and

the processing element is further connected to a second neighbor processing element that is immediately adjacent the first neighbor processing element, wherein a second output selector of the second neighbor processing element is connected to the input of the processing element; and

wherein a register of the processing element is settable to set the first output selector or the second output selector to provide a respective output to the input of the processing element.

2. The processing device of claim 1 , wherein:

the processing element is further connected to an opposite first neighbor processing element that is immediately adjacent the processing element on a side opposite the first neighbor processing element; and

the processing element is further connected to an opposite second neighbor processing element that is immediately adjacent the opposite first neighbor processing element.

3. The processing device of claim 2 , wherein the processing element is further connected to a third neighbor processing element that is immediately adjacent the second neighbor processing element.

4. The processing device of claim 3 , wherein the processing element is further connected to an opposite third neighbor processing element that is immediately adjacent the opposite second neighbor processing element.

5. The processing device of claim 4 , wherein each non-endmost processing element of the array of processing elements is connected to neighboring processing elements in a same relative manner as the processing element.

6. The processing device of claim 4 , wherein the processing element includes an input selector to select input to the processing element as one of:

the first neighbor processing element,

the opposite first neighbor processing element,

the second neighbor processing element,

the opposite second neighbor processing element,

the third neighbor processing element, and

the opposite third neighbor processing element.

7. The processing device of claim 6 , wherein the input selector comprises an unbalanced multiplexer arrangement.

8. The processing device of claim 1 , wherein each processing element includes an input selector to select input to the processing element as a respective output of a respective output selector of one of the neighboring processing elements.

9. The processing device of claim 8 , wherein the register controls both the setting of the output selector of a selected one of the neighboring processing elements and the setting of the input selector of the processing element.

10. The processing device of claim 1 , further comprising:

a controller connected to the array of processing elements, the controller to perform a rearrangement of data within the array of processing elements by controlling communication of the data through the interconnections among the array of processing elements.

11. The processing device of claim 10 , further comprising:

memory at the array of processing elements;

wherein the controller is to control the array of processing elements to perform a single-instruction, multiple-data (SIMD) operation with data in the memory.

12. The processing device of claim 1 , further comprising a plurality of the arrays of processing elements.

13. A computing device comprising a plurality of processing devices of claim 1 as an arrangement of banks.

14. A non-transitory machine-readable medium comprising executable instructions to:

load a matrix of coefficients into an array of processing elements as serialized coefficients;

load an input vector into the array of processing elements; and

perform an operation with the matrix of coefficients and the input vector by:

performing a parallel operation with the serialized coefficients in the array of processing elements and the input vector;

accumulating a result vector; and

rotating the input vector in the array of processing elements and repeating the performing of the parallel operation and the accumulating until the operation is complete, wherein rotating the input vector includes controlling an input selector at a processing element and controlling an output selector at a neighbor processing element to deliver an element of the input vector to the processing element; and

when the operation is complete, outputting the result vector.

15. A processing device comprising:

an array of processing elements, each processing element including an arithmetic logic unit to perform an operation;

interconnections among the array of processing elements to provide direct communication among neighboring processing elements of the array of processing elements wherein:

a processing element of the array of processing elements is connected to a neighbor processing element via an input selector of the processing element and an output selector of the neighbor processing element to selectively take output of the neighbor processing element as input to the processing element, wherein the input selector of the processing element and the output selector of the neighbor processing element are settable by a register of the processing element.

16. The processing device of claim 15 , wherein the input selector includes an unbalanced multiplexer arrangement.