Memory device to suspend ROM operation and a method of operating the memory device

1. A memory device, comprising:

a read only memory (ROM) address controller configured to sequentially output a plurality of operation ROM addresses at which original ROM codes to be executed in response to an operation command are stored, and configured to suspend output of the plurality of operation ROM addresses in response to a suspend signal;

a suspend signal generator configured to generate the suspend signal; and

a register configured to, in response to an external command, store a time code indicating a preset period and store a ROM address code indicating a suspend ROM address,

wherein the suspend signal is activated during the preset period, depending on whether the suspend ROM address is identical to an operation ROM address, among the plurality of operation ROM addresses, currently being output, and

wherein the suspend ROM address is an address of a ROM code selected from among the original ROM codes according to whether execution is suspended.

2. The memory device according to claim 1 , further comprising:

a ROM address decoder configured to provide the suspend ROM address obtained by decoding the ROM address code to the suspend signal generator.

3. The memory device according to claim 2 , wherein:

the register is configured to store code values indicating operating conditions of the memory device, and

the external command includes at least one of a set parameter command and a set feature command for setting code values stored in the register.

4. The memory device according to claim 2 , further comprising:

a ROM data storage circuit configured to store the original ROM codes indicating an operation algorithm of the memory device;

a command interface configured to decode the operation command, and then to provide a start ROM address, among the plurality of operation ROM addresses, to the ROM address controller; and

an operation controller configured to acquire, from the ROM data storage circuit, a ROM code corresponding to the operation ROM address currently being output and provide the ROM code to the ROM address controller.

5. The memory device according to claim 4 , wherein the ROM address controller is configured to determine an operation ROM address to be output next to the operation ROM address currently being output, among the plurality of operation ROM addresses, based on the ROM code corresponding to the operation ROM addresses.

6. The memory device according to claim 1 , wherein the ROM address controller is configured to output the plurality of operation ROM addresses in synchronization with an internal clock.

7. The memory device according to claim 1 , wherein the ROM address controller is configured to:

suspend output of the plurality of operation ROM addresses in response to the suspend signal having an active level, and

resume the output of the plurality of operation ROM addresses when a level of the suspend signal makes a transition from the active level to an inactive level.

8. The memory device according to claim 1 , wherein the suspend signal generator comprises:

an address comparator configured to, depending on whether the suspend ROM address is identical to the operation ROM address currently being output, output an enable signal having any one of an active level and an inactive level; and

a timer circuit configured to output the suspend signal having any one of an active level and an inactive level in response to the enable signal.

9. The memory device according to claim 8 , wherein the address comparator is configured to, when the suspend ROM address is identical to the operation ROM address, output the enable signal having an active level.

10. The memory device according to claim 9 , wherein the timer circuit is configured to output the suspend signal having an active level during the preset period in response to the enable signal having an active level.

11. The memory device according to claim 10 , wherein the timer circuit is configured to operate in synchronization with an internal clock and is configured to count a preset number of clocks based on the time code indicating the preset period and then to output the suspend signal during the preset period.

12. The memory device according to claim 8 , wherein the address comparator is configured to, when the suspend ROM address is different from the operation ROM address currently being output, output the enable signal having an inactive level.

13. The memory device according to claim 12 , wherein the timer circuit is configured to output the suspend signal having an inactive level in response to the enable signal having an inactive level.

14. The memory device according to claim 4 , wherein the operation controller is further configured to generate an operation signal and page buffer control signals based on ROM codes corresponding to the plurality of operation ROM addresses, wherein the operation signal is a signal for performing a memory operation corresponding to the operation command.

15. The memory device according to claim 14 , further comprising:

a plurality of memory blocks;

a voltage generator configured to generate operating voltages for an operation of the memory device in response to the operation signal;

a read and write circuit configured to include page buffers coupled to the plurality of memory blocks through bit lines and to control voltages that are applied to the bit lines in response to the page buffer control signals;

an address decoder configured to transfer the operating voltages to a memory block selected from among the plurality of memory blocks based on an address; and

an input/output circuit configured to exchange the operation command, the address, and the data with a memory controller.

16. The memory device according to claim 14 , wherein the memory operation comprises at least one of a read operation, a program operation, and an erase operation.

17. A method of operating a memory device, the memory device storing original ROM codes indicating an operation algorithm of the memory device, the method comprising:

receiving a suspend time through an external command;

sequentially reading a plurality of operation ROM addresses at which ROM codes corresponding to a memory operation, among the original ROM codes, are stored;

determining whether an operation ROM address currently being read, among the plurality of operation ROM addresses, is identical to a suspend ROM address; and

suspending, based on a result of the determination, an operation of the memory device being executed based on a ROM code corresponding to the operation ROM address currently being read during the suspend time,

wherein the suspend ROM address is an address of a ROM code selected from among the original ROM codes according to whether execution is suspended.

18. The method according to claim 17 , further comprising:

resuming, when the suspend time has elapsed, a remaining memory operation starting from a suspended operation in the memory operation.

19. The method according to claim 18 , wherein resuming the remaining memory operation comprises:

sequentially reading remaining operation ROM addresses starting from the operation ROM address currently being read, among the plurality of operation ROM addresses; and

performing an operation of the memory device based on ROM codes corresponding to the remaining operation ROM addresses.

20. The method according to claim 17 , further comprising:

receiving the suspend ROM address through the external command.