Cache hit ratio simulation using a partial data set

1. A non-transitory tangible computer readable storage medium having stored thereon a computer program for implementing a method of cache hit ratio simulation using a partial data set, the computer program including a set of instructions which, when executed by a computer, cause the computer to perform a method comprising the steps of:

determining a set of sampled addresses, the set of sampled addresses being a subset of all addresses of a storage system of a storage environment, the set of sampled addresses being fewer than all addresses of the storage system and being taken across a full address range of the storage system;

monitoring read IO operations on the set of sampled addresses;

maintaining a sequential table containing sequential information for the sampled addresses to keep track of whether read IO operations on the sampled addresses are associated with sequential read IO operations;

implementing, by a simulation engine, a cache simulation using only the set of sampled addresses, the simulation engine using a cache management algorithm to determine a cache hit ratio of the set of sampled addresses, the cache management algorithm being also used by a cache manager to place a portion of the addresses of the storage system into cache during a runtime operation, the cache management algorithm being configured to pre-fetch addresses to the cache in connection with sequential memory access operations and being configured to not pre-fetch addresses to the cache in connection with memory access operations to non-sequential memory addresses;

using the sequential table, by the simulation engine, to determine when read IO operations on the set of sampled addresses are part of sequential read IO operations;

determining a quantity of memory access operations to frequently accessed addresses in the set of sampled addresses; and

correcting, by the simulation engine, the cache hit ratio of the set of sampled addresses on the cache simulation based on the quantity of memory access operations to the frequently accessed addresses in the set of sampled addresses.

2. The non-transitory tangible computer readable storage medium of claim 1 , wherein the step of using the sequential table, by the simulation engine, comprises checking the sequential table by the simulation engine, for each read IO operation, to determine if the read IO operation is a sequential read IO operation.

3. The non-transitory tangible computer readable storage medium of claim 1 , wherein the step of maintaining the sequential table further comprises purging addresses from the sequential table after a timeout threshold.

4. The non-transitory tangible computer readable storage medium of claim 1 , further comprising the step of adjusting cache size allocations based on a corrected cache hit ratio from the simulation engine.

5. The non-transitory tangible computer readable storage medium of claim 1 , further comprising: periodically determining a new set of sampled addresses, and using the new set of sampled addresses for a simulation iteration interval.

6. The non-transitory tangible computer readable storage medium of claim 5 , wherein, within the simulation iteration interval, the method further comprises the step of periodically receiving updated actual cache size and actual hit ratio information of the storage system.

7. The non-transitory tangible computer readable storage medium of claim 6 :

wherein periodically receiving updated actual cache size and actual hit ratio information of the storage system occurs multiple times within the simulation iteration interval to obtain snapshots during the simulation iteration interval, and

wherein at least a subset of the snapshots are averaged over time.

8. The non-transitory tangible computer readable storage medium of claim 1 , wherein the subset of all addresses is between 0.1% and 2% of all addresses of the storage system.

9. A storage environment, comprising:

a cache;

a storage system; and

a cache manager, the cache manager using a cache management algorithm to place a portion of the addresses of the storage system into cache during a runtime operation; and

a simulation engine, the simulation engine implementing control logic, which when executed on a processor, cause the processor to implement a method of cache simulation using a portion of the addresses of the storage system, the method including the steps of:

determining a set of sampled addresses, the set of sampled addresses being a subset of all addresses of the storage system, the set of sampled addresses being fewer than all addresses of the storage system and being taken across a full address range of the storage system;

monitoring read IO operations on the set of sampled addresses;

maintaining a sequential table containing sequential information for the sampled addresses to keep track of whether read IO operations on the sampled addresses are associated with sequential read IO operations;

implementing, by the simulation engine, a cache simulation using only the set of sampled addresses, the simulation engine using a cache management algorithm to determine a cache hit ratio of the set of sampled addresses, the cache management algorithm being also used by a cache manager to place a portion of the addresses of the storage system into cache during a runtime operation, the cache management algorithm being configured to pre-fetch addresses to the cache in connection with sequential memory access operations and being configured to not pre-fetch addresses to the cache in connection with memory access operations to non-sequential memory addresses;

using the sequential table, by the simulation engine, to determine when read IO operations on the set of sampled addresses are part of sequential read IO operations;

determining a quantity of memory access operations to frequently accessed addresses in the set of sampled addresses; and

correcting, by the simulation engine, the cache hit ratio of the set of sampled addresses on the cache simulation based on the quantity of memory access operations to the frequently accessed addresses in the set of sampled addresses.

10. The storage environment of claim 9 , wherein the step of using the sequential table, by the simulation engine, comprises checking the sequential table by the simulation engine, for each read IO operation, to determine if the read IO operation is a sequential read IO operation.

11. The storage environment of claim 9 , wherein the step of maintaining the sequential table further comprises purging addresses from the sequential table after a timeout threshold.

12. The storage environment of claim 9 , further comprising the step of adjusting cache size allocations based on a corrected cache hit ratio from the simulation engine.

13. The storage environment of claim 9 , further comprising: periodically determining a new set of sampled addresses, and using the new set of sampled addresses for a simulation iteration interval.

14. The storage environment of claim 13 , wherein, within the simulation iteration interval, the method further comprises the step of periodically receiving updated actual cache size and actual hit ratio information of the storage system.

15. The storage environment of claim 14 :

wherein periodically receiving updated actual cache size and actual hit ratio information of the storage system occurs multiple times within the simulation iteration interval to obtain snapshots during the simulation iteration interval, and

wherein at least a subset of the snapshots are averaged over time.

16. The storage environment of claim 9 , wherein the subset of all addresses is between 0.1% and 2% of all addresses of the storage system.