Semiconductor device performing row hammer refresh operation
Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-di vision manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.
1. An apparatus comprising:
a memory cell array including a plurality of word lines each coupled to a plurality of memory cells; and
a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command,
wherein a first number of the plurality of word lines are selected in response to the first internal signal, and
wherein a second number of the plurality of word lines are selected in response to the second internal signal, the second number is smaller than the first number.
2. The apparatus of claim 1 , further comprising:
a first address storing circuit storing an address signal updated in response to the first internal signal;
a second address storing circuit storing an address signal updated in response to an access history of the memory cell array; and
a row logic circuit configured to select the first number of the plurality of word lines corresponding to the address signal supplied from the first address storing circuit in response to the first internal signal, and to select the second number of the plurality of word lines corresponding to the address signal supplied from the second address storing circuit in response to the second internal signal.
3. The apparatus of claim 2 ,
wherein the memory cell array is divided into a plurality of memory mats,
wherein the row logic circuit is configured to simultaneously select the first number of word lines each belonging to a respective one of the plurality of memory mats in response to the first internal signal, and
wherein the row logic circuit is configured to select one of the word lines belonging to one of the plurality of memory mats in response to the second internal signal.
4. The apparatus of claim 3 ,
wherein the first number of the plurality of word lines are selected during a first time period,
wherein the second number of the plurality of word lines are selected during a second time period, and
wherein the first and second time periods do not overlap with each other.
5. The apparatus of claim 4 , wherein the second number of another word line of the plurality of word lines corresponding to the address signal supplied from the second address storing circuit is selected in response to the first internal signal during the first time period.
6. The apparatus of claim 4 , wherein the first number of other word lines of the plurality of word lines corresponding to the address signal supplied from the first address storing circuit are selected in response to the second internal signal during the second time period.
7. The apparatus of claim 1 , wherein when a control signal is in a first state, the control circuit is configured to activate the first and second internal signals in a time-division manner in response to a first occurrence of the first external command, and is configured to activate the second internal signal twice without activating the first internal signal in response to a second occurrence of the first external command.
8. The apparatus of claim 1 , wherein when a control signal is in a second state, the control circuit is configured to activate the first and second internal signals in a time-division manner in response to a first occurrence of the first external command, and is configured to activate the first internal signal once without activating the second internal signal in response to a second occurrence of the first external command.
9. The apparatus of claim 1 , wherein the first external command is a per-bank refresh command.
10. The apparatus of claim 1 ,
wherein the memory cell array is divided into a plurality of memory banks including first and second memory banks,
wherein the control circuit is configured to activate the first and second internal signals in a time-division manner and to activate third and fourth internal signals in a time-division manner in response to a second external command,
wherein the first number of the plurality of word lines in the first memory bank are selected in response to the first internal signal,
wherein the second number of the plurality of word lines in the first memory bank are selected in response to the second internal signal,
wherein the first number of the plurality of word lines in the second memory bank are selected in response to the third internal signal, and
wherein the second number of the plurality of word lines in the second memory bank are selected in response to the fourth internal signal.
11. The apparatus of claim 10 ,
wherein the first number of the plurality of word lines in the first memory bank are selected during a first time period,
wherein the second number of the plurality of word lines in the first memory bank are selected during a second time period,
wherein the first number of the plurality of word lines in the second memory bank are selected during a third time period,
wherein the second number of the plurality of word lines in the second memory bank are selected during a fourth time period,
wherein the first and second time periods do not overlap with each other, and
wherein the third and fourth time periods do not overlap with each other.
12. The apparatus of claim 11 , wherein the second and third time periods partially overlap with each other.
13. The apparatus of claim 11 , wherein the second and fourth time periods are identical with each other.
14. The apparatus of claim 10 , wherein the second external command is an all-bank refresh command.
15. An apparatus comprising:
a memory cell array including a plurality of word lines each coupled to a plurality of memory cells; and
a control circuit configured to activate a first internal signal in response to a first external command,
wherein the memory cell array is divided into first and second groups,
wherein a first number of the plurality of word lines in the first group are selected in response to the first internal signal, and
wherein a second number of the plurality of word lines in the second group are selected in response to the first internal signal, the second number is smaller than the first number.
16. The apparatus of claim 15 , wherein the first number of the plurality, of word lines in the first group and the second number of the plurality of word lines in the second group are simultaneously selected in response to the first internal signal.
17. The apparatus of claim 15 ,
wherein the control circuit is configured to activate a second internal signal after activating the first internal signal in response to the first external command,
wherein the first number of the plurality of word lines in the second group are selected in response to the second internal signal, and
wherein the second number of the plurality of word lines in the first group are selected in response to the second internal signal.
18. An apparatus comprising:
a memory cell array including a plurality of word lines each coupled to a plurality of memory cells;
a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command;
a first address storing circuit storing an address signal that is updated in response to the first internal signal;
a second address storing circuit storing an address signal that is updated in response to an access history of the memory cell array; and
a row logic circuit configured to select one or more word lines corresponding to the address signal supplied from the first address storing circuit in response to the first internal signal, and to select one or more word lines corresponding to the address signal supplied from the second address storing circuit in response to the second internal signal.
19. The apparatus of claim 18 , wherein when a control signal is in a first state, the control circuit is configured to activate the first and second internal signals in a time-division manner in response to a first occurrence of the first external command, and is configured to activate the second internal signal twice without activating the first internal signal in response to a second occurrence of the first external command.
20. The apparatus of claim 18 , wherein when a control signal is in a second state, the control circuit is configured to activate the first and second internal signals in a time-division manner in response to a first occurrence of the first external command, and is configured to activate the first internal signal once without activating the second internal signal in response to a second occurrence of the first external command.