Base station, terminal, and wireless communication system

1. A base station comprising:

a first processor circuit; and

a second processor circuit configured to processes a wireless signal, wherein

the first processor circuit includes

a third processor circuit configured to processes a control signal, and

a fourth processor circuit configured to processes user data, and wherein

the third processor circuit shares, with the fourth processor circuit, a second terminal identifier used in user-data processing performed in the second processor circuit and the fourth processor circuit, and wherein

when, from a first higher-level device, a first terminal identifier and a higher-level identifier identifying a second higher-level device that performs user-data processing are fed, the third processor circuit requests the second terminal identifier from the fourth processor circuit and feeds, to the second processor circuit, the second terminal identifier allocated by the fourth processor circuit, and

the fourth processor circuit allocates the second terminal identifier to the third processor circuit, and wherein

when the first terminal identifier is fed from the first higher-level device, the third processor circuit requests the second terminal identifier from the fourth processor circuit and feeds, to the second processor circuit, the second terminal identifier allocated by the fourth processor circuit and transmits an allocation response to the fourth processor circuit upon establishment of a communication path to a terminal, and

when the second terminal identifier is requested by the third processor circuit, the fourth processor circuit allocates the second terminal identifier to the third processor circuit and cancels the allocation of the second terminal identifier to the third processor circuit upon no reception of the allocation response from the third processor circuit.

2. The base station according to claim 1 , wherein

the third processor circuit receives allocation of the second terminal identifiers from the fourth processor circuit in advance before communication with a terminal is started, and

the fourth processor circuit allocates the second terminal identifier to the third processor circuit before communication with the terminal is started.

3. The base station according to claim 2 , wherein

when a first terminal identifier is fed from the first higher-level device, the third processor circuit feeds, to the second processor circuit, the second terminal identifier selected from among the second terminal identifiers allocated by the fourth processor circuit.

4. The base station according to claim 1 , wherein

the third processor circuit generates the second terminal identifier used in user-data processing performed in the second processor circuit and the fourth processor circuit by using a first terminal identifier and the higher-level identifier fed from the first higher-level device.

5. The base station according to claim 4 , wherein

the higher-level identifier is address information of a second higher-level device, and

the third processor circuit generates the second terminal identifier by connecting the first terminal identifier and the address information of the second higher-level device fed from the first higher-level device.

6. The base station according to claim 1 , wherein

the third processor circuit acquires, from each fourth processor circuit, information related to a second higher-level device with which the fourth processor circuit is connectable, selects the fourth processor circuit that executes processing of user data with a terminal from among a plurality of the fourth processor circuits based on the acquired information, and feeds, to the second processor circuit, the second terminal identifier used in user-data processing performed in the second processor circuit and the selected fourth processor circuit.

7. A terminal that performs communication with a base station including a first processor circuit and a second processor circuit that processes a wireless signal, the terminal comprising:

a communication unit that associates a first terminal identifier and a second terminal identifier, the first terminal identifier being fed from a first higher-level device to a third processor circuit that processes a control signal among a plurality of first processor circuits, the second terminal identifier corresponding to a higher-level identifier identifying a second higher-level device that performs user-data processing, the communication unit being configured to perform transmission and reception, in accordance with the second terminal identifier, with the second processor circuit that relays communication with a fourth processor circuit that processes user data among the plurality of first processor circuits and wherein

when, from the first higher-level device, the first terminal identifier and the higher-level identifier identifying the second higher-level device that performs user-data processing are fed, the third processor circuit requests the second terminal identifier from a fourth processor circuit and feeds, to the second processor circuit, the second terminal identifier allocated by the fourth processor circuit, and

the fourth processor circuit allocates the second terminal identifier to the third processor circuit, and wherein

when the first terminal identifier is fed from the first higher-level device, the third processor circuit requests the second terminal identifier from the fourth processor circuit and feeds, to the second processor circuit, the second terminal identifier allocated by the fourth processor circuit and transmits an allocation response to the fourth processor circuit upon establishment of a communication path to a terminal, and

when the second terminal identifier is requested by the third processor circuit, the fourth processor circuit allocates the second terminal identifier to the third processor circuit and cancels the allocation of the second terminal identifier to the third processor circuit upon no reception of the allocation response from the third processor circuit.

8. A wireless communication system including a base station, a terminal, a first higher-level device that manages communication of the terminal, and a second higher-level device that performs user-data processing, wherein

the base station includes

a first processor circuit; and

a second processor circuit configured to processes a wireless signal, wherein

the first processor circuit includes

a third processor circuit configured to processes a control signal, and

a fourth processor circuit configured to processes user data, and wherein

the third processor circuit shares, with the fourth processor circuit, a second terminal identifier used in user-data processing performed in the second processor circuit and the fourth processor circuit, and wherein

when, from a first higher-level device, a first terminal identifier and a higher-level identifier identifying a second higher-level device that performs user-data processing are fed, the third processor circuit requests the second terminal identifier from the fourth processor circuit and feeds, to the second processor circuit, the second terminal identifier allocated by the fourth processor circuit, and

the fourth processor circuit allocates the second terminal identifier to the third processor circuit, and wherein

when the first terminal identifier is fed from the first higher-level device, the third processor circuit requests the second terminal identifier from the fourth processor circuit and feeds, to the second processor circuit, the second terminal identifier allocated by the fourth processor circuit and transmits an allocation response to the fourth processor circuit upon establishment of a communication path to a terminal, and

when the second terminal identifier is requested by the third processor circuit, the fourth processor circuit allocates the second terminal identifier to the third processor circuit and cancels the allocation of the second terminal identifier to the third processor circuit upon no reception of the allocation response from the third processor circuit.