IP Library Granted Patent US 11,165,014
Granted Patent B2
US 11,165,014 · App. 16/825,008 · Granted Nov 2, 2021

Semiconductor device

Inventors: Yohei Ogawa (Chiba, JP); Hirotaka Uemura (Chiba, JP)
Assignee: ABLIC INC.
H01L43/04H01L43/065
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Quick Facts
Patent No.
US 11,165,014
App. No.
16/825,008
Granted
Nov 2, 2021
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate; a vertical Hall element including a magnetosensitive portion, and formed in the semiconductor substrate; and an excitation wiring provided above a surface of the semiconductor substrate and apart from the magnetosensitive portion. The excitation wiring is formed of a single wiring with a plurality of turns. The excitation wiring includes a plurality of main wiring portions arranged side by side, and apart from one another in an overlapping region that overlaps the magnetosensitive portion as viewed in plan view from a direction orthogonal to the surface of the semiconductor substrate; and auxiliary wiring portions connecting each of the plurality of main wiring portions to one another in series.

Claims (15)

1. A semiconductor device comprising:

a semiconductor substrate;

a vertical Hall element having a magnetosensitive portion, and formed in the semiconductor substrate; and

an excitation wiring provided above a surface of the semiconductor substrate and apart from the magnetosensitive portion,

the excitation wiring comprising a single wiring with a plurality of turns,

the single wiring of the excitation wiring having:

a plurality of main wiring portions arranged side by side and apart from one another in an overlapping region that overlaps the magnetosensitive portion as viewed in a plan view from a direction orthogonal to the surface of the semiconductor substrate; and

auxiliary wiring portions connecting each of the plurality of main wiring portions to one another in series and arranged in a non-overlapping region outside the magnetosensitive portion as viewed in the plan view,

wherein portions of the auxiliary wiring portions parallel to the plurality of main wiring portions as viewed in the plan view are arranged to sandwich the magnetosensitive portion, and

the width of the plurality of main wiring portions is smaller than the width of the magnetosensitive portion, in a direction in which the plurality of main wiring portions are separated.

2. The semiconductor device according to claim 1 , wherein each of the plurality of main wiring portions is arranged along a direction parallel to the surface of the semiconductor substrate.

3. The semiconductor device according to claim 1 , wherein each of the plurality of main wiring portions is arranged along the direction orthogonal to the surface of the semiconductor substrate.

4. The semiconductor device according to claim 1 , wherein at least a part of the auxiliary wiring portions is arranged closer to the surface of the semiconductor substrate than a main wiring portion closest to the surface of the semiconductor substrate among the plurality of main wiring portions.

5. The semiconductor device according to claim 1 , wherein the excitation wiring includes a plurality of the single wirings.

6. The semiconductor device according to claim 1 , wherein a distance between the excitation wiring other than the main wiring portions is wider than a distance between the main wiring portions.

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2020
From: OGAWA, YOHEI; UEMURA, HIROTAKA
To: ABLIC INC.
Reel/Frame 052177/0945 →
Priority Claims (2)
JP JP2019-065217 · Mar 29, 2019 · national
JP JP2020-010560 · Jan 27, 2020 · national
Continuity (1)
Related Publication 20200313079A1 · Oct 1, 2020