Memory device and test method thereof
A semiconductor system includes: a first semiconductor device suitable for outputting a command; and a second semiconductor device suitable for activating a test enable signal based on the command, generating a counting signal representing a toggling number of a row active signal for an activation period of the test enable signal, increasing and outputting an address when the counting signal reaches a target activation number, and deactivating the test enable signal when the counting signal reaches the target activation number and the address has a maximum value.
1. A semiconductor system comprising:
a first semiconductor device configured to output a first command and a second command; and
a second semiconductor device including:
an address generation circuit configured to generate a counting signal representing a toggling number of a row active signal based on a test enable signal, and increase and output an address whenever the counting signal reaches a target activation number;
a first reset signal generation circuit configured to generate a first reset signal when the counting signal reaches the target activation number while the address has a maximum value;
a first latch circuit configured to output a latch signal which is set in response to the second command and reset in response to the first reset signal;
a second reset signal generation circuit configured to generate a second reset signal when the counting signal reaches the target activation number while the latch signal is activated;
a second latch circuit configured to output the test enable signal which is set in response to the first command and reset in response to the second reset signal; and
an internal command generation circuit configured to generate the row active signal that toggles for an activation period of the test enable signal.
2. The semiconductor system of claim 1 , wherein the address generation circuit includes:
a counter reset circuit configured to generate a counter reset signal which is activated for a predetermined period at a rising edge of the test enable signal or a falling edge of a match signal;
an active counter that is reset based on the counter reset signal and counts the toggling number of the row active signal to generate the counting signal;
a match signal generation circuit configured to generate the match signal when the target activation number matches the counting signal; and
an address counter configured to increase and output the address when the match signal is inputted.
3. A semiconductor system comprising:
a first semiconductor device configured to output a command; and
a second semiconductor device including:
an address generation circuit configured to generate a counting signal representing a toggling number of a row active signal based on a test enable signal, and increase and output an address whenever the counting signal reaches a target activation number;
a termination signal generation circuit configured to generate a termination signal when the counting signal reaches the target activation number while the address has a maximum value;
a latch configured to output the test enable signal which is set in response to the command and reset in response to the termination signal; and
an internal command generation circuit configured to generate the row active signal that toggles for an activation period of the test enable signal.
4. The semiconductor system of claim 3 , wherein the internal command generation circuit suspends generation of the row active signal based on the termination signal.
5. A memory device comprising:
an address generation circuit configured to generate a counting signal representing a toggling number of a row active signal based on a test enable signal, and increase and output an address whenever the counting signal reaches a target activation number;
a first reset signal generation circuit configured to generate a first reset signal when the counting signal reaches the target activation number while the address has a maximum value;
a first latch circuit configured to output a latch signal which is set in response to a second command inputted after a first command and reset in response to the first reset signal;
a second reset signal generation circuit configured to generate a second reset signal when the counting signal reaches the target activation number while the latch signal is activated;
a second latch circuit configured to output the test enable signal which is set in response to the first command and reset in response to the second reset signal;
an internal command generation circuit configured to generate the row active signal that toggles for an activation period of the test enable signal; and
a row control circuit coupled to a memory array region through a plurality of word lines, and configured to activate and deactivate a word line corresponding to the address in response to the row active signal.
6. The memory device of claim 5 , wherein the address generation circuit includes:
a counter reset circuit configured to generate a counter reset signal which is activated for a predetermined period at a rising edge of the test enable signal or a falling edge of a match signal;
an active counter that is reset based on the counter reset signal, and counts the toggling number of the row active signal to generate the counting signal;
a match signal generation circuit configured to generate the match signal when the target activation number matches the counting signal; and
an address counter configured to increase and output the address when the match signal is inputted.
7. The memory device of claim 5 , wherein the internal command generation circuit includes:
a cycle signal generation circuit configured to generate a cycle signal that toggles when the test enable signal is inputted;
a clock counter configured to count the cycle signal to generate a cycle counting signal; and
a timing adjustment circuit configured to adjust timing of the cycle counting signal based on timing parameters to generate the row active signal.
8. The memory device of claim 7 , wherein the timing parameters include a row cycle time (tRC) and a row active time (tRAS).
9. A memory device comprising:
an address generation circuit configured to generate a counting signal representing a toggling number of a row active signal based on a test enable signal, and increase and output an address whenever the counting signal reaches a target activation number;
a termination signal generation circuit configured to generate a termination signal when the counting signal reaches the target activation number while the address has a maximum value;
a latch configured to output the test enable signal which is set in response to the command and reset in response to the termination signal;
an internal command generation circuit configured to generate the row active signal that toggles for an activation period of the test enable signal; and
a row control circuit coupled to a memory array region through a plurality of word lines, and configured to activate and deactivate a word line corresponding to the address in response to the row active signal.
10. The memory device of claim 9 , wherein the internal command generation circuit includes:
a cycle signal generation circuit configured to generate a cycle signal that toggles when the test enable signal is inputted;
a clock counter configured to count the cycle signal to generate a preliminary cycle counting signal;
a masking circuit configured to mask the preliminary cycle counting signal based on the termination signal to output a cycle counting signal; and
a timing adjustment circuit configured to adjust timing of the cycle counting signal based on timing parameters to generate the row active signal.