Finite automata global counter in a data flow graph-driven analytics platform having analytics hardware accelerators

1. An integrated circuit, comprising:

a memory including a finite automata (FA) graph, wherein the FA graph includes a plurality of nodes connected by directional arcs, wherein:

each arc representing transitions between nodes of the FA graph based on criteria specified for the respective arc,

the plurality of nodes including a skip node and a root node;

the directional arcs include an arc from the skip node to the root node; and

one or more hardware-based regular expression (RegEx) accelerators connected to the memory, wherein each RegEx accelerator includes a regular expression engine, the regular expression engine configured to receive the FA graph from the memory and to perform a regular expression operation on a stream of data units based on the received FA graph by initially traversing the root node,

wherein the regular expression engine is further configured to, a to reaching the skip node, consume a predefined number of data units in the stream of data units before traversing the arc from the skip node to the root node, wherein the predefined number of data units is provided by a counter used to detect an end of a payload.

2. The integrated circuit of claim 1 , wherein the regular expression engine is a deterministic finite automata (DFA) engine and the received FA graph is a DFA graph, and

wherein the regular expression engine is further configured to remain at the skip node consuming data units received from the stream of data units until the counter indicates an Nth data unit has been consumed.

3. The integrated circuit of claim 2 , wherein the regular expression engine loads a global counter value M into a global counter and decrements the global counter each time a data unit is received from the stream of data units, transitioning to another node when M=−0.

4. The integrated circuit of claim 2 , wherein the regular expression engine clears a global counter and increments the global counter each time a data unit is received from the stream of data units, transitioning to another node when the global counter is equal to a global counter value of M.

5. The integrated circuit of claim 1 , wherein the regular expression engine is a non-deterministic finite automata (NFA) engine and the received FA graph is an NFA graph, and

wherein the regular expression engine is further configured to remain at the skip node consuming data units received from the stream of data units until the counter indicates an Nth data unit has been consumed.

6. The integrated circuit of claim 5 , wherein the regular expression engine loads a global counter value M into a global counter and decrements the global counter each time a data unit is received from the stream of data units, transitioning to another node when M=0.

7. The integrated circuit of claim 5 , wherein the regular expression engine clears a global counter and increments the global counter each time a data unit is received from the stream of data units, transitioning to another node when the global counter is equal to a global counter value of M.

8. The integrated circuit of claim 1 , wherein the regular expression engine is a deterministic finite automata (DFA) engine and the received FA graph is a DFA graph, and

wherein the regular expression engine is further configured to remain at the skip node consuming data units received from the stream of data units until the regular expression engine encounters an end marker in the data stream.

9. The integrated circuit of claim 1 , wherein the regular expression engine is a non-deterministic finite automata (NFA) engine and the received FA graph is an NFA graph, and

wherein the regular expression engine is further configured to remain at the skip node consuming data units received from the stream of data units until the regular expression engine encounters an end marker in the data stream.

10. The integrated circuit of claim 1 , wherein the integrated circuit further comprises one or more programmable processor cores, wherein the programmable processor cores are communicatively coupled to the memory.

11. The integrated circuit of claim 1 , wherein the integrated circuit further comprises a cluster manager and one or more programmable processor cores, wherein the programmable processor cores are communicatively coupled to the cluster manager and to the memory.

12. A method, comprising:

receiving a regular expression operation to be performed on a stream of data units;

expressing the regular expression operation as a finite automata (FA) graph, the FA graph having a plurality of nodes connected by directional arcs, wherein:

each arc representing transitions between nodes of the FA graph based on criteria specified for the respective arc,

the plurality of nodes including nodes, including a skip node and a root node, representing states in the regular expression operation, and

the directional arcs include an arc from the skip node to the root node; and

performing the regular expression operation on the stream of data units based on the FA graph, wherein performing includes configuring a regular expression engine of a hardware-based regular expression accelerator to:

beginning at the root node in the plurality of nodes of the FA graph, step the regular expression engine through one or more nodes of the FA graph until the regular expression engine arrives at the skip node; and

consume, at the skip node, a predefined number of data units from the stream of data units before traversing the arc from the skip node to the root node, wherein the predefined number of data units is provided by a counter used to detect an end of a payload.

13. The method of claim 12 , wherein receiving the regular expression operation to be performed on a stream of data units includes receiving a data flow graph.

14. The method of claim 12 , wherein the regular expression engine is a deterministic finite automata (DFA) engine and the FA graph is a DFA graph, and

wherein the regular expression engine is further configured to remain at the skip node consuming data units received from the stream of data units until the counter indicates an Nth data unit has been consumed.

15. The method of claim 14 , wherein the regular expression engine is further configured to perform a global counter operation terminating the regular expression operation after consuming M data units, where M is greater than N.

16. The method of claim 12 , wherein the regular expression engine is a non-deterministic finite automata (NA) engine and the received FA graph is an NFA graph, and

wherein the regular expression engine is further configured to remain at the skip node consuming data units received from the stream of data units until the counter indicates an Nth data unit has been consumed.

17. The method of claim 12 , wherein the regular expression engine is a deterministic finite automata (DFA) engine and the FA graph is a DFA graph, and

wherein the regular expression engine is further configured to remain at the skip node consuming data units received from the stream of data units until the regular expression engine encounters an end marker in the data stream.

18. The method of claim 12 , wherein the regular expression engine is a non-deterministic finite automata (NFA) engine and the received FA graph is an NFA graph, and

wherein the regular expression engine is further configured to remain at the skip node consuming data units received from the stream of data units until the regular expression engine encounters an end marker in the data stream.

19. In an integrated circuit having a regular expression engine, a method, comprising:

receiving a DFA NRA graph, the received graph including a plurality of nodes connected by directional arcs, wherein:

each arc representing transitions between nodes based on criteria specified for the respective arc,

the plurality of nodes including nodes, including a skip node and a root node, representing states in the regular expression operation, and

the directional arcs include an arc from the skip node to the root node;

selecting a stream of data units;

beginning at the root node in the plurality of nodes of the received DFA car NFA graph, stepping a regular expression engine through one or more nodes of the graph until the regular expression engine arrives at the skip node;

if the skip node is configured to consume on match, consuming, at the skip node, a predefined number of data units from the selected stream of data units before traversing the arc from the skip node to the root node, wherein the predefined number of data units is provided by a counter used to detect an end of a payload; and

if the skip node is configured to not consume on match, traversing the arc from the skip node to the root node.

20. The method of claim 15 , wherein the global counter operation is finished after operations on N data units from the stream of data units.

21. The method of claim 15 , wherein the global counter operation is finished after operations on N data units from the stream of data units, wherein the N data units are not consecutive data units.

22. The method of claim 15 , wherein the global counter operation is finished after operations of N data units from the stream of data units, wherein N=PL−IL, wherein PL is payload length in data units and IL is a number of data units operated on in a separate arc within the global counter operation.

23. A system comprising:

a processor coupled to Ea memory that stores instructions and a regular expression (RegEx) engine configured to detect patterns within a stream of data units, wherein the instructions, upon execution by the processor, cause the processor to:

receive a request to perform an analytical operation on data from the stream of data units, the analytical operation specifying a query having at least one query predicate,

wherein, in response to the request, the controller configures the RegEx engine to operate according to one or more non-deterministic finite automata (NFA) to evaluate the query predicate by applying one or more regular expressions to the stream of data units,

wherein configuring the RegEx engine includes generating a set of NFA instructions, the NFA instructions including at least one FORK instruction, each FORK instruction having a plurality of execution paths, including a default execution path and one or more other execution paths, and programming the RegEx engine to operate according to the NFA instructions; and

wherein the RegEx engine executes the at least one FORK instruction by attaching a first stack identifier to the default execution path, pushing the default execution path and the first stack identifier to an instruction stack, attaching a second stack identifier to the other execution paths, the second stack identifier a function of the first stack identifier, pushing the other execution paths with their respective second stack identifiers to the instruction stack, and executing each execution path in order by popping the execution path from the instruction stack.

24. A method comprising:

receiving a request specifying at least one analytical operation to be performed on data, the analytical operation specifying a query having at least one query predicate;

in response to the request, configuring a regular expression (RegEx) engine to input the data as one or more streams of data units and to evaluate the query predicate against the data by applying one or more regular expressions to the one or more data streams according to one or non-deterministic finite automata (NFA), wherein configuring the RegEx engine includes generating a set of NFA instructions, the NFA instructions including at least one FORK instruction, each FORK instruction having a plurality of execution paths, including a default execution path and one or more other execution paths, and programming the RegEx engine to operate according to the NFA instructions;

executing the at least one FORK instruction, wherein executing includes:

attaching a first stack identifier to the default execution path;

pushing the default execution path and the first stack identifier to an instruction stack;

attaching a second stack identifier to the other execution paths, the second stack identifier a function of the first stack identifier;

pushing each other execution path with a respective second stack identifier to the instruction stack; and

executing each execution path in order by popping the execution path from the instruction stack.

25. The method of claim 24 , wherein the first stack identifier is determined as a function of a row identifier.