Pipelined pointwise convolution using per-channel convolution operations

1. A processor system, comprising:

a hardware channel convolution processor unit configured to perform a portion of a depthwise convolution, including by being configured to:

multiply each data element of a first group of data elements of a plurality of channels of a portion of a convolution data matrix with a corresponding data element of a second group of data elements of a plurality of depthwise convolution weight matrices to determine a corresponding multiplication result of multiplication results; and

for each specific channel of the plurality of channels, sum together ones of the multiplication results corresponding to the specific channel to determine one corresponding channel convolution result data element in a corresponding channel convolution result matrix to calculate a portion of depthwise convolution results; and

a hardware dot product processor unit configured to perform at least a portion of a pointwise convolution, including by being configured to apply pointwise weight matrices to the portion of depthwise convolution results calculated using the hardware channel convolution processor unit to determine a portion of separable convolution results while at least another portion of the depthwise convolution results is being calculated in parallel by the hardware channel convolution processor unit of the processor system;

wherein the hardware channel convolution processor unit and the hardware dot product processor unit are different hardware units and the portion of depthwise convolution results is provided from the hardware channel convolution processor unit to the hardware dot product processor unit for pipeline processing.

2. The system of claim 1 , further comprising a first processing element and a second processing element, and wherein the first processing element includes the hardware channel convolution processor unit and the second processing element includes the hardware dot product processor unit.

3. The system of claim 1 , wherein a total count of the data elements of the first group is the same as a total count of the data elements of the second group.

4. The system of claim 1 , wherein the hardware channel convolution processor unit comprises a plurality of calculation units and each calculation unit of the plurality of calculation units is configured to receive a plurality of data elements of the first group corresponding to a same channel of the convolution data matrix and a plurality of corresponding data elements of the second group corresponding to a separate convolution weight matrix for the same channel of the convolution data matrix.

5. The system of claim 4 , wherein each calculation unit of the plurality of calculation units includes a different vector multiply unit and a different vector adder unit.

6. The system of claim 5 , wherein each of the different vector adder units includes a different adder tree.

7. The system of claim 1 , wherein the convolution data matrix is a three-dimensional machine learning data matrix.

8. The system of claim 1 , further comprising a data input unit configured to: process the data elements of the first group by channel into a plurality of data input vectors, wherein each of the plurality of data input vectors includes data elements corresponding to a two-dimensional sub-matrix of the convolution data matrix.

9. The system of claim 1 , further comprising a weight input unit configured to: process the data elements of the second group into a plurality of weight input vectors, wherein each of the plurality of weight input vectors includes data elements corresponding to one of the plurality of depthwise convolution weight matrices.

10. The system of claim 1 , wherein each of the plurality of depthwise convolution weight matrices is a 3×3, 5×5, 7×7, 9×9, or 11×11 matrix.

11. The system of claim 1 , wherein the data elements of the first group are 4-bit, 8-bit, 2-byte, or 4-byte elements.

12. The system of claim 1 , wherein a total count of the data elements of the first group is a multiple of a cache line size.

13. The system of claim 1 , wherein a total count of the pointwise weight matrices is a multiple of a cache line size.

14. The system of claim 1 , wherein the portion of depthwise convolution results calculated using the hardware channel convolution processor unit is stored in a local memory of a processing element.

15. The system of claim 1 , wherein the portion of depthwise convolution results calculated using the hardware channel convolution processor unit to determine the portion of separable convolution results has a width and height dimension of 1×1.

16. The system of claim 15 , wherein a depth dimension of the portion of depthwise convolution results calculated using the hardware channel convolution processor unit to determine the portion of separable convolution results is a multiple of a cache line size of a memory.

17. The system of claim 1 , wherein the convolution data matrix, the plurality of depthwise convolution weight matrices, the portion of depthwise convolution results, the pointwise weight matrices, and the portion of separable convolution results are arranged in a depth-first layout format.

18. A method, comprising:

receiving a three-dimensional convolution operation instruction specifying a convolution data matrix;

identifying separate convolution operations from the received three-dimensional convolution operation instruction;

using a hardware channel convolution processor unit to:

perform a depthwise convolution operation with a portion of the convolution data matrix and a plurality of depthwise convolution weight matrices; and

determine a portion of depthwise convolution results; and

using a hardware dot product processor unit to:

perform a pipelined pointwise convolution operation using the portion of depthwise convolution results and a plurality of pointwise weight matrices while at least another portion of the depthwise convolution results is being calculated in parallel by the hardware channel convolution processor unit; and

determine separable convolution results;

wherein the hardware channel convolution processor unit and the hardware dot product processor unit are different hardware units and the portion of depthwise convolution results is provided from the hardware channel convolution processor unit to the hardware dot product processor unit for pipeline processing.

19. The method of claim 18 , further comprising storing the separable convolution results to a memory location using a same layout format as the convolution data matrix.

20. A method, comprising:

for each data element of a first group of data elements of a plurality of channels of a portion of a convolution data matrix, multiplying at a hardware channel convolution processor unit the data element of the first group of data elements with a corresponding data element of a second group of data elements of a plurality of depthwise convolution weight matrices to determine a corresponding multiplication result of multiplication results;

for each specific channel of the plurality of channels, summing together at the hardware channel convolution processor unit ones of the multiplication results corresponding to the specific channel to determine one corresponding channel convolution result data element in a corresponding channel convolution result matrix to calculate a portion of depthwise convolution results;

transmitting the portion of depthwise convolution results from the hardware channel convolution processor unit to a hardware dot product processor unit for pipeline processing; and

applying at the hardware dot product processor unit pointwise weight matrices to the portion of depthwise convolution results calculated using the hardware channel convolution processor unit to determine a portion of separable convolution results while at least another portion of the depthwise convolution results is being calculated in parallel by the hardware channel convolution processor unit;

wherein the hardware channel convolution processor unit and the hardware dot product processor unit are different hardware units U.