IP Library Granted Patent US 11,038,538
Granted Patent B2
US 11,038,538 · App. 16/827,355 · Granted Jun 15, 2021

Maximum likelihood error detection for decision feedback equalizers with PAM modulation

Inventors: Jamal Riani (Fremont, CA); Farshid Rafiee Rad (Los Gatos, CA); Benjamin P. Smith (Ottawa, CA); Yu Liao (Longmont, CO); Sudeep Bhoja (San Jose, CA)
Assignee: INPHI CORPORATION
H03M13/3916H03M13/3911H04L1/0058H04L1/0054
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Quick Facts
Patent No.
US 11,038,538
App. No.
16/827,355
Granted
Jun 15, 2021
Kind
B2
Abstract

The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.

Claims (11)

1. An error detection device comprising:

a decision feedback equalizer (DFE) configured to remove intersymbol interference (ISI) noise from a data signal and generate DFE decisions;

an error detector configured to detect error events associated with a sequence of data of the DFE decisions by performing maximum likelihood detections, the error detector being configured to generate an output error states; and

an enable logic configured to generate a control signal for the error detector based on a quality of the data signal.

2. The device of claim 1 further comprising a feedforward equalizer (FFE) configured to equalize the data signal.

3. The device of claim 1 wherein the error detector removes burst errors associated with the DFE decisions.

4. The device of claim 1 wherein the DFE comprises a reduced-state trellis path that comprises an intrinsic variable for storing signs of errors.

5. The device of claim 1 wherein the error detector is configured to store signs associated with an input error state and generate an output error states by flipping the signs.

6. The device of claim 1 further comprising a de-mapping module for processing the data signal.

7. The device of claim 1 wherein the DFE comprises a reduced-state trellis path that comprises two input states and two output states.

8. The device of claim 1 wherein the error detector is configured to flip signs using a reduced-state trellis path.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2020
From: RIANI, JAMAL; RAD, FARSHID RAFIEE; SMITH, BENJAMIN; LIAO, YU; BHOJA, SUDEEP
To: INPHI CORPORATION
Reel/Frame 052211/0543 →