High voltage blocking III-V semiconductor device

1. A method of forming a semiconductor device, comprising:

providing a base substrate of type IV semiconductor material comprising a rear surface and an upper surface opposite the rear surface;

forming first and second device areas in the base substrate that are electrically isolated from one another and each extend to the upper surface;

forming a first region of type III-V semiconductor material on the base substrate over the first device area;

forming a second region of type III-V semiconductor material on the base substrate over the second device area, the second region of type III-V semiconductor material being laterally electrically insulated from the first region of type III-V semiconductor material;

integrally forming a first high-electron mobility transistor in the first region of type III-V semiconductor material;

integrally forming a second high-electron mobility transistor in the second region of type III-V semiconductor material, the first and second high-electron mobility transistors each comprising source and drain terminals and are each configured to control a conductive connection between the respective source and drain terminals;

connecting the first and second high-electron mobility transistors in series with the source terminal of the first high-electron mobility transistor connected to the drain terminal of the second high-electron mobility transistor;

connecting the source terminal of the first high-electron mobility transistor high-electron mobility transistor electrically to the electrically to the first device area; and

forming a voltage blocking device that electrically isolates the first device area from a subjacent region of the base substrate,

wherein the voltage blocking device is formed by no more than two masked dopant implantation steps.

2. The method of claim 1 , wherein the base substrate has an intrinsic dopant concentration of a first conductivity type, and wherein forming the voltage blocking device comprises:

performing a first masked implantation step that forms a second doped well in a region of the base substrate, the second doped well having a second conductivity type that is opposite the first conductivity type.

3. The method of claim 2 , wherein forming the voltage blocking device further comprises:

performing a second masked implantation step that forms a first doped well within the second doped well, the first doped well having the first conductivity type and having a higher dopant concentration than the region of the base substrate, and

wherein the first and second masked implantation steps form a first two-way voltage blocking device that is interposed between the first device area and the subjacent region of the base substrate.

4. A method of forming a semiconductor device, comprising:

providing a base substrate of type IV semiconductor material comprising a rear surface and an upper surface opposite the rear surface;

forming first and second device areas in the base substrate that are electrically isolated from one another and each extend to the upper surface;

forming a first region of type III-V semiconductor material on the base substrate over the first device area;

forming a second region of type III-V semiconductor material on the base substrate over the second device area, the second region of type III-V semiconductor material being laterally electrically insulated from the first region of type III-V semiconductor material;

integrally forming a first high-electron mobility transistor in the first region of type III-V semiconductor material,

integrally forming a second high-electron mobility transistor in the second region of type III-V semiconductor material, the first and second high-electron mobility transistors each comprising source and drain terminals and are each configured to control a conductive connection between the respective source and drain terminals;

connecting the first and second high-electron mobility transistors in series with the source terminal of the first high-electron mobility transistor connected to the drain terminal of the second high-electron mobility transistor;

connecting the source terminal of the first high-electron mobility transistor electrically to the first device area;

forming one or more epitaxial layers on a region of the base substrate; and

forming an isolation trench between the first and second device areas, and

wherein the one or more epitaxial layers form a voltage blocking device that electrically isolates the first device area from the region of the base substrate.

5. The method of claim 4 , wherein forming the one or more epitaxial layers comprises:

epitaxially forming a first epitaxial layer of a second conductivity type directly on the region of the base substrate, the second conductivity type being opposite the first conductivity type, and

wherein the voltage blocking device comprises a second p-n junction diode between the first epitaxial layer and the region of the base substrate.

6. The method of claim 5 , wherein forming the one or more epitaxial layers further comprises:

epitaxially forming a second epitaxial layer of the first conductivity type on the first epitaxial layer, the second epitaxial layer having a higher dopant concentration than the region of the base substrate, and

wherein the voltage blocking device further comprises a first p-n junction diode between the first and second epitaxial layers.

7. The method of claim 6 , wherein the isolation trench is formed to extend through the first and second epitaxial layers, and wherein the first device area is fully surrounded by the isolation trench.