IP Library Granted Patent US 11,500,815
Granted Patent B2
US 11,500,815 · App. 16/830,418 · Granted Nov 15, 2022

Dual relationship-based hash structure for non-volatile memory technology

Inventors: Gopal Singh (Lucknow, IN); Pooja Singh (Bangalore, IN); Rahul D. Vishwakarma (Bangalore, IN); Shelesh Chopra (Bangalore, IN)
Assignee: EMC IP Holding Company LLC
G06F16/137G06F16/1734G06F16/182G06F16/24554H04L9/0894
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Quick Facts
Patent No.
US 11,500,815
App. No.
16/830,418
Granted
Nov 15, 2022
Kind
B2
Abstract

Methods, apparatus, and processor-readable storage media for implementing dual relationship-based hash structures for non-volatile memory technology are provided herein. An example computer-implemented method includes generating a hash storage structure by: creating multiple layers of storage components, wherein a first layers comprise a first number of storage components and at least a second layer comprises at least a second number of storage components less than the first number of storage components; configuring the at least a second layer to share at least a portion of the storage components therein with at least a portion of the storage components in the first layer; partitioning each of the storage components in each of the multiple layers into multiple portions; configuring a respective status value space for each of the multiple portions of each of the storage components in the multiple layers; and implementing the hash storage structure in at least one storage system.

Claims (51)

1. A computer-implemented method comprising:

generating a hash storage structure by:

creating multiple layers of storage components, wherein a first of the multiple layers comprises a first number of storage components and wherein at least a second of the multiple layers comprises at least a second number of storage components, wherein the at least a second number of storage components is less than the first number of storage components;

configuring the at least a second of the multiple layers to share at least a portion of the storage components therein with at least a portion of the storage components in the first layer;

partitioning each of the storage components in each of the multiple layers into multiple portions; and

configuring a respective status value space for each of the multiple portions of each of the storage components in the multiple layers;

implementing the generated hash storage structure in at least one storage system; and

responsive to at least one specified condition, resizing the generated hash storage structure and implementing the resized generated hash storage structure in the at least one storage system, wherein resizing comprises inserting an additional layer of one or more storage components to the generated hash storage structure, wherein the additional layer of one or more storage components comprises a different number of storage components than at least one of the multiple layers;

wherein the method is performed by at least one processing device comprising a processor coupled to a memory.

2. The computer-implemented method of claim 1 , further comprising:

expanding the resized generated hash storage structure by inserting a second additional layer of storage components to the resized generated hash structure, wherein the second additional layer comprises a number of storage components that is greater than the first number of storage components contained within the first of the multiple layers.

3. The computer-implemented method of claim 2 , wherein the first of the multiple layers comprises N storage components, wherein a second of the multiple layers comprises N/2 storage components, and wherein the second additional layer comprises 2N storage components.

4. The computer-implemented method of claim 2 , wherein expanding the generated hash storage structure comprises:

mapping data from a last of the multiple layers to the second additional layer; and

rendering the last of the multiple layers eligible for storage.

5. The computer-implemented method of claim 1 , wherein the additional layer comprises a number of one or more storage components that is less than a number of storage components contained within a last of the multiple layers.

6. The computer-implemented method of claim 5 , wherein resizing the generated hash storage structure comprises:

mapping data from the first of the multiple layers to the additional layer; and

rendering the first of the multiple layers eligible for storage.

7. The computer-implemented method of claim 1 , wherein configuring the at least a second of the multiple layers comprises configuring a second of the multiple layers to share one of the storage components therein with at least two storage components in the first layer.

8. The computer-implemented method of claim 1 , wherein configuring the at least a second of the multiple layers comprises configuring data to be written to in a given one of the storage components of a second of the multiple layers upon a determination that a first of the storage components in the first layer is full, wherein the given one of the storage components of the second layer is also shared with at least a second of the storage components in the first layer.

9. The computer-implemented method of claim 1 , wherein each of the multiple portions is configured to store one key-value pair.

10. The computer-implemented method of claim 1 , wherein a one byte-length status register is associated with each of the storage components in each of the multiple layers.

11. The computer-implemented method of claim 1 , wherein the status value space comprises a space for at least one of a value indicating that the respective portion of the storage component is available for a write operation and a value indicating that the respective portion of the storage component holds a key-value pair.

12. The computer-implemented method of claim 1 , wherein the first of the multiple layers comprises N storage components, and wherein a second of the multiple layers comprises N/2 storage components.

13. A non-transitory processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code when executed by at least one processing device causes the at least one processing device:

to generate a hash storage structure by:

creating multiple layers of storage components, wherein a first of the multiple layers comprises a first number of storage components and wherein at least a second of the multiple layers comprises at least a second number of storage components, wherein the at least a second number of storage components is less than the first number of storage components;

configuring the at least a second of the multiple layers to share at least a portion of the storage components therein with at least a portion of the storage components in the first layer;

partitioning each of the storage components in each of the multiple layers into multiple portions; and

configuring a respective status value space for each of the multiple portions of each of the storage components in the multiple layers;

to implement the generated hash storage structure in at least one storage system; and

responsive to at least one specified condition, to resize the generated hash storage structure and implement the resized generated hash storage structure in the at least one storage system, wherein resizing comprises inserting an additional layer of one or more storage components to the generated hash storage structure, wherein the additional layer of one or more storage components comprises a different number of storage components than at least one of the multiple layers.

14. The non-transitory processor-readable storage medium of claim 13 , wherein the program code when executed by the at least one processing device causes the at least one processing device:

to expand the resized generated hash storage structure by inserting a second additional layer of storage components to the resized generated hash structure, wherein the second additional layer comprises a number of storage components that is greater than the first number of storage components contained within the first of the multiple layers.

15. The non-transitory processor-readable storage medium of claim 13 , wherein the additional layer comprises a number of one or more storage components that is less than a number of storage components contained within a last of the multiple layers.

16. The non-transitory processor-readable storage medium of claim 13 , wherein configuring the at least a second of the multiple layers comprises configuring a second of the multiple layers to share one of the storage components therein with at least two storage components in the first layer.

17. An apparatus comprising:

at least one processing device comprising a processor coupled to a memory;

the at least one processing device being configured:

to generate a hash storage structure by:

creating multiple layers of storage components, wherein a first of the multiple layers comprises a first number of storage components and wherein at least a second of the multiple layers comprises at least a second number of storage components, wherein the at least a second number of storage components is less than the first number of storage components;

configuring the at least a second of the multiple layers to share at least a portion of the storage components therein with at least a portion of the storage components in the first layer;

partitioning each of the storage components in each of the multiple layers into multiple portions; and

configuring a respective status value space for each of the multiple portions of each of the storage components in the multiple layers;

to implement the generated hash storage structure in at least one storage system; and

responsive to at least one specified condition, to resize the generated hash storage structure and implement the resized generated hash storage structure in the at least one storage system, wherein resizing comprises inserting an additional layer of one or more storage components to the generated hash storage structure, wherein the additional layer of one or more storage components comprises a different number of storage components than at least one of the multiple layers.

18. The apparatus of claim 17 , wherein the at least one processing device being further configured:

to expand the resized generated hash storage structure by inserting a second additional layer of storage components to the resized generated hash structure, wherein the second additional layer comprises a number of storage components that is greater than the first number of storage components contained within the first of the multiple layers.

19. The apparatus of claim 17 , wherein the additional layer comprises a number of one or more storage components that is less than a number of storage components contained within a last of the multiple layers.

20. The apparatus of claim 17 , wherein configuring the at least a second of the multiple layers comprises configuring a second of the multiple layers to share one of the storage components therein with at least two storage components in the first layer.

Assignments (11)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052852/0022) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0582 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0917) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0509 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0081) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0441 →
RELEASE OF SECURITY INTEREST AT REEL 052771 FRAME 0906 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0298 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 23, 2020
From: SINGH, GOPAL; SINGH, POOJA; VISHWAKARMA, RAHUL D.; CHOPRA, SHELESH
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 054443/0001 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052852/0022 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0917 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0081 →
SECURITY AGREEMENT Recorded May 28, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052771/0906 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
Continuity (1)
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