IP Library Granted Patent US 11,157,378
Granted Patent B2
US 11,157,378 · App. 16/831,334 · Granted Oct 26, 2021

Method, device, data storage system, and computer product for error injection

Inventor: Min Zhang (Shanghai, CN)
Assignee: EMC IP Holding Company LLC
G06F11/2215G06F11/0772G06F11/0775G06F11/1076G06F11/221
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Quick Facts
Patent No.
US 11,157,378
App. No.
16/831,334
Granted
Oct 26, 2021
Kind
B2
Abstract

Error injection techniques involve, while a data storage system is in an error injection mode, injecting information representing an error of a storage device array into a first switch, such that the information representing the error is passed from a first downstream port of the first switch to a computing device through a second switch, the first and second switches being connected to the storage device array via downstream ports, and the first downstream port being connected to a second downstream port of the second switch; and determining error handling capability of the data storage system by obtaining a handling result of the information representing the error from the computing device. Accordingly, errors from storage devices can be simulated to facilitate detecting error handling in the entire I/O path comprehensively.

Claims (47)

1. A method for error injection, comprising:

while a data storage system is in an error injection mode, injecting information representing an error of a storage device array of the data storage system into a first switch of the data storage system, such that the information representing the error is passed from a first downstream port of the first switch, through a second switch of the data storage system, to a computing device connected with the second switch, the first switch and the second switch being connected to the storage device array via respective downstream ports, and the first downstream port being connected to a second downstream port of the second switch in the error injection mode; and

determining error handling capability of the data storage system by obtaining a handling result of the information representing the error by the computing device.

2. The method of claim 1 , wherein injecting the information representing the error comprises:

configuring the first downstream port to operate as an upstream port of the first switch;

injecting the information representing the error at the first downstream port, the first downstream port being connected with a third downstream port of the first switch in the error injection mode; and

causing the computing device to perform an I/O operation for a storage device in the storage device array that is connected with the third downstream port, to pass the information representing the error to the computing device.

3. The method of claim 2 , wherein injecting the information representing the error at the first downstream port comprises:

in response to user specification in the error injection mode, injecting the information representing the error at the first downstream port.

4. The method of claim 1 , wherein the first switch and the second switch are comprised in a Just a Bunch of Disks (JBOD) Array Enclosure.

5. The method of claim 1 , wherein the first switch and the second switch are Peripheral Component Interface Express (PCIe) switches.

6. The method of claim 1 , wherein injecting the information representing the error includes:

providing the information representing the error into the first switch of the data storage system while a normal paddle card of the data storage system, which does not connect the first downstream port with the second downstream port, is replaced with a short-circuited paddle card that connects the first downstream port with the second downstream port.

7. An electronic device, comprising:

a processor; and

a memory coupled to the processor and storing instructions for execution, the instructions, when executed by the processor, causing the electronic device to perform acts comprising:

while a data storage system is in an error injection mode, injecting information representing an error of a storage device array of the data storage system into a first switch of the data storage system, such that the information representing the error is passed from a first downstream port of the first switch, through a second switch of the data storage system, to a computing device connected with the second switch, the first switch and the second switch being connected to the storage device array via respective downstream ports, and the first downstream port being connected to a second downstream port of the second switch in the error injection mode; and

determining error handling capability of the data storage system by obtaining a handling result of the information representing the error from the computing device.

8. The device of claim 7 , wherein injecting the information representing the error comprises:

configuring the first downstream port to operate as an upstream port of the first switch;

injecting the information representing the error at the first downstream port, the first downstream port being connected with a third downstream port of the first switch in the error injection mode; and

causing the computing device to perform an I/O operation for a storage device in the storage device array that is connected with the third downstream port, to pass the information representing the error to the computing device.

9. The device of claim 8 , wherein injecting the information representing the error at the first downstream port comprises:

in response to user specification in the error injection mode, injecting the information representing the error at the first downstream port.

10. The device of claim 7 , wherein the first switch and the second switch are comprised in a Just a Bunch of Disks (JBOD) Array Enclosure.

11. The device of claim 7 , wherein the first switch and the second switch are Peripheral Component Interface Express (PCIe) switches.

12. A data storage system, comprising:

a storage device array;

a computing device; and

a first switch and a second switch being connected to the storage device array via respective downstream ports, the second switch being connected to the computing device via upstream ports,

wherein, in an error injection mode of the data storage system, the first switch is injected with information representing an error of the storage device array of the data storage system, a first downstream port of the first switch and a second downstream port of the second switch being connected such that the information representing the error is passed from the first switch to the second switch, which in turn passes the information representing the error to the computing device.

13. The data storage system of claim 12 , wherein the first downstream port is configured to operate as an upstream port of the first switch and to receive the information representing the error injected in the error injection mode; and

wherein the first downstream port is connected with a third downstream port of the first switch, and after the information representing the error are injected, the computing device performs an I/O operation for a storage device in the storage device array that is connected with the third downstream port.

14. The data storage system of claim 13 , wherein in the error injection mode, a fourth downstream port of the second switch is connected with a fifth downstream port of the first switch, and the fourth downstream port is configured to operate as an upstream port of the second switch and is connected with a sixth downstream port of the second switch which is in turn connected to the storage device that is connected with the third downstream port.

15. The data storage system of claim 12 , wherein the first switch and the second switch are comprised in a Just a Bunch of Disks (JBOD) Array Enclosure.

16. The data storage system of claim 12 , wherein the first switch and the second switch are Peripheral Component Interface Express (PCIe) switches.

17. A computer program product having a non-transitory computer-readable medium which stores a set of instructions, the set of instructions, when executed, causing a device to perform a method of:

while a data storage system is in an error injection mode, injecting information representing an error of a storage device array of the data storage system into a first switch of the data storage system, such that the information representing the error is passed from a first downstream port of the first switch, through a second switch of the data storage system, to a computing device connected with the second switch, the first switch and the second switch being connected to the storage device array via respective downstream ports, and the first downstream port being connected to a second downstream port of the second switch in the error injection mode; and

determining error handling capability of the data storage system by obtaining a handling result of the information representing the error at the computing device.

18. The computer program product of claim 17 , wherein the computer-executable instructions, when executed, causing the device to:

configure the first downstream port to operate as an upstream port of the first switch;

inject the information representing the error at the first downstream port, the first downstream port being connected with a third downstream port of the first switch in the error injection mode; and

cause the computing device to perform an I/O operation for a storage device in the storage device array that is connected with the third downstream port, to pass the information representing the error to the computing device.

19. The computer program product of claim 18 , wherein the computer-executable instructions, when executed, causing the device to:

in response to user specification in the error injection mode, inject the information representing the error at the first downstream port.

20. The computer program product of claim 17 , wherein the first switch and the second switch are comprised in a Just a Bunch of Disks (JBOD) Array Enclosure.

21. The computer program product of claim 17 , wherein the first switch and the second switch are Peripheral Component Interface Express (PCIe) switches.

Assignments (11)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0081) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0441 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0917) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0509 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052852/0022) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0582 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052771 FRAME 0906 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0298 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0917 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0081 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052852/0022 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2020
From: ZHANG, MIN
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 052795/0924 →
SECURITY AGREEMENT Recorded May 28, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052771/0906 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →