Chip tampering detector

1. A chip, comprising:

an integrated circuit disposed on a first chip layer, the integrated circuit including a plurality of protected areas;

a plurality of resistor-capacitor circuits, wherein each resistor-capacitor circuit of the plurality of resistor-capacitor circuits includes a capacitor disposed on a second chip layer that at least partially covers a corresponding protected area of the plurality of protected areas and wherein each capacitor of the plurality of resistor-capacitor circuits is configured to change a time-constant of a corresponding resistor-capacitor circuit upon being physically altered; and

an anti-tampering circuit configured to sense a plurality of time-constants of the plurality of resistor-capacitor circuits to determine that at least one capacitor of a plurality of capacitors of the plurality of resistor-capacitor circuits has been physically altered.

2. The chip according to claim 1 , wherein a resistor-capacitor circuit of the plurality of resistor-capacitor circuits further includes:

a resistor coupled between an input and an output of the resistor-capacitor circuit; and

a capacitor having a first electrode coupled to the output of the resistor-capacitor circuit, a second electrode coupled to a ground voltage, and an insulator disposed between the first electrode and the second electrode.

3. The chip according to claim 2 , wherein:

the first electrode has a first plurality of finger portions;

the second electrode has a second plurality of finger portions, the first plurality of finger portions interdigitated with and within a same plane as the second plurality of finger portions; and

the insulator includes an oxide layer disposed between interdigitated finger portions.

4. The chip according to claim 1 , wherein the anti-tampering circuit includes:

a driver circuit coupled to an input of a resistor-capacitor circuit of the plurality of resistor-capacitor circuits, the driver circuit configured to generate an input signal to probe a time-constant of the resistor-capacitor circuit; and

a counter circuit coupled to an output of the resistor-capacitor circuit, the counter circuit configured to receive an output signal from the resistor-capacitor circuit in response to the input signal, the output signal changing according to the time-constant of the resistor-capacitor circuit.

5. The chip according to claim 4 , wherein the driver circuit includes:

a digital-signal source configured to generate the input signal including a digital transition between a first signal level and a second signal level.

6. The chip according to claim 5 , wherein the digital-signal source is a latch or a flip-flop.

7. The chip according to claim 1 , wherein the anti-tampering circuit includes:

a driver circuit that includes an input-multiplexer configured to route an input signal from a digital-signal source to an input of a particular resistor-capacitor circuit of the plurality of resistor-capacitor circuits based on a state of the input-multiplexer.

8. The chip according to claim 7 , wherein the anti-tampering circuit includes:

a counter circuit that includes an output-multiplexer configured to route an output signal from the particular resistor-capacitor circuit of the plurality of resistor-capacitor circuits to a counter based on a state of the output-multiplexer.

9. The chip according to claim 8 , wherein the counter is configured to measure a time that the output signal matches one or more criteria, the time corresponding to the time-constant of the particular resistor-capacitor circuit of the plurality of resistor-capacitor circuits.

10. A system comprising:

an integrated circuit;

a plurality of resistor-capacitor circuits that each include a capacitor covering a portion of the integrated circuit, each capacitor configured to change a time-constant of a corresponding resistor-capacitor circuit when the capacitor is physically altered;

a driver circuit configured to apply an input signal to each of the plurality of resistor-capacitor circuits;

a counter circuit configured to measure a time that each output signal from each of the plurality of resistor-capacitor circuits matches at least one criterion; and

a processor configured by software instructions to detect chip tampering based on the times associated with the plurality of resistor-capacitor circuits measured by the counter circuit.

11. The system according to claim 10 , wherein the capacitor is a metal-oxide-metal capacitor having interdigitated electrodes separated by an oxide.

12. The system according to claim 10 , wherein to detect chip tampering based on the times measured by the counter circuit includes:

comparing the times that the plurality of resistor-capacitor circuits match the least one criterion.

13. The system according to claim 10 , wherein the processor is further configured by software instructions to alter data stored in a memory of the system in response to detecting chip tampering.

14. The system according to claim 10 , wherein the driver circuit includes:

a digital-signal source configured to generate the input signal including a digital transition between a first signal level and a second signal level.

15. The system according to claim 14 , wherein the digital-signal source is a latch or a flip flop.

16. The system according to claim 10 , wherein the driver circuit includes an input-multiplexer configured to route the input signal from a digital-signal source to an input of one of the plurality of resistor-capacitor circuits based on a state of the input-multiplexer.

17. The system according to claim 10 , wherein the counter circuit includes an output-multiplexer configured to route an output signal from one of the plurality of resistor-capacitor circuits to the counter circuit based on a state of the output-multiplexer.

18. The system according to claim 17 , wherein the time corresponds to a time constant of the one of the plurality of resistor-capacitor circuits.