Apparatus and method for efficient management of multi-level memory
An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory having a near memory and a far memory. The memory controller to maintain first and second caches. The first cache to cache pages recently accessed from the far memory. The second cache to cache addresses of pages recently accessed from the far memory. The second cache having a first level and a second level. The first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level. The memory controller comprising logic circuitry to inform system software that: a) a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory; and/or, b) a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.
1 . An apparatus, comprising:
a processor including an integrated memory controller to interface with a multi-level memory comprising volatile near memory comprising Dynamic Random Access Memory external to the processor and far memory comprising volatile or non-volatile memory external to the processor, the memory controller to maintain first and second caches, the first cache to cache pages recently accessed from the far memory, the memory controller to look into the first cache for pages that are mapped to the far memory before looking to the far memory for the pages that are mapped to the far memory, the second cache to cache addresses of pages recently accessed from the far memory, the second cache having a first level and a second level, the first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level, the memory controller to inform system software of either or both of a) and b) below:
a) that a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory;
b) that a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.
2 . The apparatus of claim 1 wherein the first level of the second cache is implemented on the same semiconductor chip as the memory controller.
3 . The apparatus of claim 1 wherein the memory controller includes first logic circuitry to track accesses of cache lines of the pages whose respective addresses are entered in the second cache.
4 . The apparatus of claim 3 wherein the memory controller comprises second logic circuitry to inform system software at least one of:
a) a third page having a cache line that has been accessed more than once is a candidate for migration from the far memory to the near memory; and
b) a fourth page having a threshold number of cache lines that have been accessed is a candidate for migration from the far memory to the near memory.
5 . The apparatus of claim 1 wherein the memory controller is to maintain a log that identifies pages that were migrated from far memory to near memory and then were written to in near memory after their migration.
6 . The apparatus of claim 1 wherein, the memory controller includes first logic circuitry to track accesses of cache lines of the pages whose respective addresses are entered in the second cache and second logic circuitry to inform system software that a third page having a cache line that has been accessed more than once is a candidate for migration from the far memory to the near memory, wherein, if the third page is written to after its entry into the first cache, a dirty bit for the page is asserted.
7 . The apparatus of claim 1 wherein the far memory comprises Non-Volatile Random Access Memory (NVRAM).
8 . A computing system, comprising:
a multi-level main memory comprising volatile near memory and far memory comprising volatile or non-volatile memory;
a processor, external to the multi-level main memory and including,
a plurality of processing cores; and
an integrated memory controller coupled to the multi-level main memory, the memory controller to maintain first and second caches, the first cache to cache pages recently accessed from the far memory, the second cache to cache addresses of pages recently accessed from the far memory, the memory controller to look into the first cache for pages that are mapped to the far memory before looking to the far memory for the pages that are mapped to the far memory, the second cache having a first level and a second level, the first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level, the memory controller to inform system software of either or both of a) and b) below:
a) that a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory;
b) that a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.
9 . The computing system of claim 8 wherein the first level of the second cache is implemented on the same semiconductor chip as the memory controller.
10 . The computing system of claim 8 wherein the memory controller includes first logic circuitry to track accesses of cache lines of the pages whose respective addresses are entered in the second cache.
11 . The computing system of claim 10 wherein the memory controller comprises second logic circuitry to inform system software at least one of:
a) a third page having a cache line that has been accessed more than once is a candidate for migration from the far memory to the near memory; and
b) a fourth page having a threshold number of cache lines that have been accessed is a candidate for migration from the far memory to the near memory.
12 . The computing system of claim 8 wherein the memory controller is to maintain a log that identifies pages that were migrated from far memory to near memory and then were written to in near memory after their migration.
13 . The computing system of claim 8 wherein, the memory controller includes first logic circuitry to track accesses of cache lines of the pages whose respective addresses are entered in the second cache and second logic circuitry to inform system software that a third page having a cache line that has been accessed more than once is a candidate for migration from the far memory to the near memory, wherein, if the third page is written to after its entry into the first cache, a dirty bit for the page is asserted.
14 . The computing system of claim 8 wherein the far memory comprises Non-Volatile Random Access Memory (NVRAM).
15 . A non-transitory machine readable storage medium containing program code that when processed by a computer causes the computer to perform a method, comprising:
receiving an indication from a memory controller integrated on a chip that interfaces with a multi-level memory comprising volatile near memory external to the chip and far memory comprising volatile or non-volatile memory external to the chip, the memory controller to maintain first and second caches, the first cache to cache pages recently accessed from the far memory, the memory controller to look into the first cache for pages that are mapped to the far memory before looking to the far memory for the pages that are mapped to the far memory, the second cache to cache addresses of pages recently accessed from the far memory, the second cache having a first level and a second level, the first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level, the indication being any of a) and b) below:
a) that a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory;
b) that a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.
16 . The non-transitory machine readable storage medium of claim 15 wherein the method further comprises at least one of:
in response to a) above, migrating the first page from the far memory to the near memory; and
in response to b) above, migrating the second page from the far memory to the near memory.
17 . The non-transitory machine readable storage medium of claim 16 wherein the method further comprises, after at least one of the first and second pages have been migrated from the far memory to the near memory, detecting that the at least one of the first and second pages has been written to and updating a log, wherein, the log tracks migrated pages in near memory that are dirty.
18 . The non-transitory machine readable storage medium of claim 17 wherein the method further comprises periodically reading pages listed in the log from near memory and copying them back to far memory.
19 . The non-transitory machine readable medium of claim 17 wherein the method further comprises, in response to a power loss event, reading pages listed in the log from near memory and copying them back to far memory.
20 . The non-transitory machine readable medium of claim 19 wherein the method further comprises, commensurate with the at least one of the first and second pages being migrated from the far memory to the near memory, clearing a respective dirty bit in a respective entry of a translation look aside buffer for the at least one of the first and second pages.