IP Library Granted Patent US 11,243,388
Granted Patent B2
US 11,243,388 · App. 16/833,714 · Granted Feb 8, 2022

Sampling circuit and laser scanning microscope

Inventor: Hiroyuki Yabugaki (Tokyo, JP)
Assignee: OLYMPUS CORPORATION
G02B21/008G02B21/0032H03L7/08
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,243,388
App. No.
16/833,714
Granted
Feb 8, 2022
Kind
B2
Abstract

A sampling circuit includes: a phase synchronization circuit for generating, by a phase-locked loop, an N-multiplied clock that is N times as high as the scanning frequency of a scanning position signal of a resonant scanner and is synchronized with the phase of the scanning position signal, an AD converter for AD-converting a detection signal obtained by detecting light from a sample in synchronization with the N-multiplied clock, a counter for counting the number of clocks in synchronization with the N-multiplied clock, a memory for storing a counter threshold corresponding to a desired scanning position of the resonant scanner, a comparison circuit for outputting a sampling clock in response to the counter threshold and a counter value of the counter circuit coinciding with each other, and a data processing circuit for sampling the AD-converted detection signal based on the sampling clock and generating pixel data.

Claims (25)

1. A sampling circuit comprising:

a phase synchronization circuit that generates, based on a scanning position signal indicating a scanning position of a laser light scanned on a sample by a scanner and by a phase-locked loop, an N-multiplied clock which has a frequency N times as high as a scan frequency of the scanning position signal (N represents an integer of 1 or more) and is synchronized with a phase of the scanning position signal;

an AD converter that AD-converts a detection signal obtained by converting light from the sample with a detector in synchronization with the N-multiplied clock generated by the phase synchronization circuit;

a counter that counts a number of clocks in synchronization with the N-multiplied clock;

a memory that stores at least one predetermined counter threshold of the counter corresponding to a desired scanning position by the scanner;

a comparison circuit that compares the counter threshold stored in the memory with a counter value indicating the number of clocks counted by the counter and outputs a sampling clock in response to the counter threshold and the counter value coinciding with each other; and

a data processing circuit that samples the detection signal AD-converted by the AD converter based on the sampling clock output from the comparison circuit and generates pixel data based on the sampled detection signal.

2. The sampling circuit according to claim 1 , further comprising:

a correction amount generation circuit that outputs a correction amount for correcting a shift between scanning start positions of the laser light on an outward path and a return path by the scanner; and

a counter threshold correction circuit that corrects the counter threshold stored in the memory based on the correction amount output from the correction amount generation circuit.

3. The sampling circuit according to claim 1 , wherein the data processing circuit samples only the detection signal that has been AD-converted in synchronization with an output of the sampling clock.

4. The sampling circuit according to claim 1 ,

wherein the detection signal includes a plurality of detection signals, and

wherein the data processing circuit samples the plurality of detection signals based on an output of the sampling clock, and generates the pixel data based on an integration signal obtained by integrating the plurality of sampled detection signals.

5. The sampling circuit according to claim 4 , wherein the plurality of detection signals include all detection signals that have been AD-converted during a period of time from an output of a sampling clock until an output of a next sampling clock.

6. The sampling circuit according to claim 4 , wherein the plurality of detection signals include a certain number of detection signals that have been AD-converted temporally before or after an output of the sampling clock.

7. The sampling circuit according to claim 4 , wherein the plurality of detection signals are a certain number of detection signals that have been AD-converted in a period of time that spans temporally before and after an output of the sampling clock.

8. A laser scanning microscope comprising:

the sampling circuit according to claim 1 ;

a laser light source that generates the laser light;

a microscope main body including the scanner and the detector; and

a controller that controls the sampling circuit and the scanner,

wherein the controller is configured to generate image data of the sample based on the pixel data obtained by the sampling circuit.

9. The laser scanning microscope according to claim 8 further comprising an input device that specifies a scanning range on the sample to be scanned with the laser light by the scanner,

wherein the controller is configured to calculate the counter threshold based on the scanning range specified by the input device.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2022
From: OLYMPUS CORPORATION
To: EVIDENT CORPORATION
Reel/Frame 060699/0487 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2020
From: YABUGAKI, HIROYUKI
To: OLYMPUS CORPORATION
Reel/Frame 052254/0943 →
Priority Claims (2)
JP JP2019-073240 · Apr 8, 2019 · national
JP JP2020-036710 · Mar 4, 2020 · national
Continuity (1)
Related Publication 20200319444A1 · Oct 8, 2020