IP Library Granted Patent US 11,087,784
Granted Patent B2
US 11,087,784 · App. 16/833,942 · Granted Aug 10, 2021

Data storage devices with integrated slider voltage potential control

Inventors: John Contreras (Palo Alto, CA); Yunfei Ding (Fremont, CA); Kuok San Ho (Redwood City, CA); Ian Robson McFadyen (San Jose, CA); Joey Martin Poss (Rochester, MN)
Assignee: Western Digital Technologies, Inc.
G11B5/3929G11B5/012G11B5/314G11B5/3912G11B2005/0024
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Quick Facts
Patent No.
US 11,087,784
App. No.
16/833,942
Granted
Aug 10, 2021
Kind
B2
Abstract

Disclosed herein is a data storage device comprising a recording media, a slider comprising a write head having a write-field enhancement structure for recording data to the recording media, an electronics module, and a plurality of lines disposed between and coupled to the slider and the electronics module, wherein at least one line of the plurality of lines is configured to both couple a bias voltage to a body of the slider, and carry a bias current for the write-field enhancement structure. Also disclosed herein is a data storage device comprising a slider with an embedded contact sensor, an electronics module, and a plurality of lines disposed between and coupled to the slider and the electronics module, wherein at least one line of the plurality of lines is configured to both couple a bias voltage to a body of the slider, and provide a signal to the embedded contact sensor.

Claims (35)

1. A data storage device, comprising:

a recording media;

a slider comprising a write head for recording data to the recording media, the write head including a write-field enhancement structure;

an electronics module; and

a plurality of lines disposed between and coupled to the slider and the electronics module,

wherein at least one line of the plurality of lines is configured to both (a) couple a slider bias voltage to a body of the slider to control a potential of the slider, and (b) carry a bias current for the write-field enhancement structure.

2. The data storage device recited in claim 1 , wherein the write-field enhancement structure is a spin torque oscillator (STO).

3. The data storage device recited in claim 1 , wherein the write-field enhancement structure comprises a DC field generation (DFG) layer.

4. The data storage device recited in claim 1 , wherein the bias current comprises a low-frequency component and a current kick.

5. The data storage device recited in claim 4 , wherein at least one characteristic of the low-frequency component or the current kick is programmable.

6. The data storage device recited in claim 5 , wherein the at least one characteristic comprises one or more of an amplitude, a duration, a timing, a delay, or an advance.

7. The data storage device recited in claim 4 , wherein the electronics module comprises firmware configured to determine at least an aspect of the current kick based at least in part on a resistance of the write-field enhancement structure.

8. The data storage device recited in claim 7 , wherein the electronics module is further configured to determine the resistance of the write-field enhancement structure.

9. The data storage device recited in claim 7 , wherein the at least an aspect of the current kick comprises an amplitude of the current kick.

10. The data storage device recited in claim 4 , wherein the electronics module comprises:

an analog circuit configured to determine at least an aspect of the current kick based at least in part on a resistance of the write-field enhancement structure.

11. The data storage device recited in claim 10 , wherein the analog circuit is a first analog circuit, and wherein the electronics module further comprises:

a second analog circuit configured to determine the resistance of the write-field enhancement structure.

12. The data storage device recited in claim 10 , wherein the at least an aspect of the current kick comprises an amplitude of the current kick.

13. The data storage device recited in claim 4 , wherein the electronics module comprises:

firmware configured to determine at least one of a timing, delay, advance, amplitude, or duration of the current kick.

14. The data storage device recited in claim 4 , further comprising:

a voltage source or a current source to generate the low-frequency component.

15. The data storage device recited in claim 4 , further comprising:

a current source to generate the current kick.

16. The data storage device recited in claim 1 , further comprising circuitry configured to mitigate radio-frequency interference, and wherein the at least one line of the plurality of lines is coupled to the circuitry.

17. The data storage device recited in claim 1 , further comprising a flexure disposed between the electronics module and the slider, the flexure comprising:

a support layer;

an insulator layer;

a conductor layer; and

a cover layer,

and wherein the plurality of lines is in the conductor layer.

18. The data storage device recited in claim 1 , wherein a subset of lines of the plurality of lines is configured to provide a write current to the write head to record the data to the recording media.

19. The data storage device recited in claim 1 , further comprising a push-pull differential circuit coupled to the at least one line and configured to provide the bias current to the write-field enhancement structure.

20. The data storage device recited in claim 19 , wherein the push-pull differential circuit is included in the electronics module.

Assignments (5)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0279 →
SECURITY INTEREST Recorded May 14, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053482/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2020
From: CONTRERAS, JOHN; DING, YUNFEI; HO, KUOK SAN; MCFADYEN, IAN ROBSON; POSS, JOEY MARTIN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052258/0694 →
Continuity (2)
Provisional Application 62843187 · May 3, 2019
Related Publication 20200349969A1 · Nov 5, 2020