Controller for managing superblocks and operation method thereof

1. A method for operating a controller that controls a memory device, the method comprising:

replacing a bad block of a superblock with a replacement block to form a reproduced superblock;

controlling the memory device to perform a program operation on the reproduced superblock according to an interleaving scheme;

moving data stored in the replacement block to a pseudo-replacement block when the program operation on the reproduced superblock is completed; and

releasing the replacement block from the reproduced superblock,

wherein the controlling includes:

mapping logical addresses provided along with an external request to physical addresses of memory blocks forming the reproduced superblock; and

providing program commands and data to the memory blocks forming the reproduced superblock.

2. The method of claim 1 , wherein the moving includes:

controlling the memory device to program the data stored in the replacement block to the pseudo-replacement block; and

controlling the memory device to erase the replacement block.

3. The method of claim 1 , wherein the moving is performed as a background operation.

4. The method of claim 3 , further comprising:

detecting an idle state of the memory device,

wherein the moving is performed based on a result of the detecting.

5. The method of claim 3 , further comprising:

identifying the replacement block for replacing the bad block from among multiple candidate replacement blocks,

wherein the moving of the data stored in the replacement block to the pseudo-replacement block which is different from the replacement block is performed based on the identifying.

6. The method of claim 5 , wherein the identifying includes:

determining whether the identified replacement block is of the same plane as the bad block.

7. The method of claim 1 , wherein the replacement block and the pseudo-replacement block belong to different planes.

8. A controller for controlling a memory device, the controller comprising:

a processor that includes:

a superblock manager suitable for replacing a bad block of a superblock with a replacement block to form a reproduced superblock;

a command scheduler suitable for controlling the memory device to perform a program operation on the reproduced superblock according to an interleaving scheme; and

a background operation controller suitable for moving data stored in the replacement block to a pseudo-replacement block when the program operation on the reproduced superblock is completed,

wherein the superblock manager releases the replacement block from the reproduced superblock, and

wherein the command scheduler controls the memory device to perform the program operation on the reproduced superblock according to the interleaving scheme by mapping logical addresses provided along with an external request to physical addresses of memory blocks forming the reproduced superblock and providing program commands and data to the memory blocks forming the reproduced superblock.

9. The controller of claim 8 , wherein the background operation controller moves the data stored in the replacement block to the pseudo-replacement block by controlling the memory device to program the data stored in the replacement block to the pseudo-replacement block and to erase the replacement block.

10. The controller of claim 8 , wherein the background operation controller moves the data stored in the replacement block to the pseudo-replacement block based on a result of detecting an idle state of the memory device.

11. The controller of claim 8 ,

wherein the superblock manager is further suitable for identifying the replacement block from among multiple candidate reserve blocks, and

wherein the background operation controller moves the data stored in the replacement block to the pseudo-replacement block based on a result of the identifying.

12. The controller of claim 11 , wherein the superblock manager determines whether the replacement block is of the same plane as the bad block.

13. The controller of claim 8 , further comprising:

a memory suitable for storing superblock information and replacement block information.

14. The controller of claim 13 , wherein the superblock manager forms the reproduced superblock by determining whether or not the superblock includes a bad block based on the superblock information, detecting the replacement block in the replacement block pool, and replacing the bad block with the replacement block.

15. The controller of claim 8 , wherein the replacement block and the pseudo-replacement block are of different planes.