Integrated memory assemblies comprising multiple memory array decks

1. An integrated memory assembly, comprising:

a first memory array deck over a second memory array deck;

a first series of conductive lines extending across the first memory array deck, and a second series of conductive lines extending across the second memory array deck;

a first conductive line of the first series and a first conductive line of the second series being coupled with a first component through a first conductive path;

a second conductive line of the first series and a second conductive line of the second series being coupled with a second component through a second conductive path; and

the first and second conductive lines of the first series extending through first isolation circuitry to the first and second conductive paths, respectively.

2. The integrated memory assembly of claim 1 wherein the first isolation circuitry includes a first transistor which gatedly connects the first conductive line of the first series to the first conductive path, and including a second transistor which gatedly connects the second conductive line of the first series to the second conductive path.

3. The integrated memory assembly of claim 2 , wherein the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.

4. The integrated memory assembly of claim 1 , further comprising second isolation circuitry comprising a third transistor which gatedly connects the first conductive line of the second series to the first conductive path.

5. The integrated memory assembly of claim 1 wherein the conductive lines of the first and second series are wordlines.

6. The integrated memory assembly of claim 1 wherein the conductive lines of the first and second series are bitlines.

7. The integrated memory assembly of claim 1 wherein the conductive lines of the first and second series are bitlines; and further comprising:

a third series of conductive lines extending across the first memory array deck, and a fourth series of conductive lines extending across the second memory array deck; the conductive lines of the third and fourth series being wordlines.

8. The integrated memory assembly of claim 1 wherein the first and second memory array decks include 1T-1C memory cells.

9. The integrated memory assembly of claim 1 wherein the first and second memory array decks include 2T-2C memory cells.

10. The integrated memory assembly of claim 1 wherein the first and second memory array decks include 3T-1C memory cells.

11. The integrated memory assembly of claim 1 wherein the first and second memory array decks include 2T-1C memory cells.

12. A method of forming an integrated memory assembly, comprising:

forming a first memory array deck A over a second memory array deck B;

forming a first series of bitlines along the first memory array deck A, the first series of bitlines including paired comparative bitlines BL-T-A 1 and BL-C-A 1 , and paired comparative bitlines BL-T-A 2 and BL-C-A 2 ;

forming a second series of bitlines along the second memory array deck B, the second series of bitlines including paired comparative bitlines BL-T-B 1 and BL-C-B 1 , and paired comparative bitlines BL-T-B 2 and BL-C-B 2 ;

coupling the paired comparative bitlines BL-T-A 1 and BL-C-A 1 with a first sense amplifier through a first BL-T conductive path and a first BL-C conductive path, respectively;

coupling the paired comparative bitlines BL-T-A 2 and BL-C-A 2 with a second sense amplifier through a second BL-T conductive path and a second BL-C conductive path, respectively;

coupling the paired comparative bitlines BL-T-B 1 and BL-C-B 1 with the first sense amplifier through the first BL-T conductive path and the first BL-C conductive path, respectively;

coupling the paired comparative bitlines BL-T-B 2 and BL-C-B 2 with the second sense amplifier through the second BL-T conductive path and the second BL-C conductive path, respectively; and

wherein the bitlines BL-T-A 1 , BL-C-A 1 , BL-T-A 2 and BL-C-A 2 are formed to extend through first isolation circuitry to the first BL-T conductive path, the first BL-C conductive path, the second BL-T conductive path and the second BL-C conductive path, respectively; the first isolation circuitry including a first transistor which gatedly connects BL-T-A 1 to the first BL-T conductive path, a second transistor which gatedly connects BL-C-A 1 to the first BL-C conductive path, a third transistor which gatedly connects BL-T-A 2 to the second BL-T conductive path, and a fourth transistor which gatedly connects BL-C-A 2 to the second BL-C conductive path; the gates of the first, second, third and fourth second transistors being coupled with a first bitline isolation driver.

13. The method of claim 12 , wherein the bitlines BL-T-B 1 , BL-C-B 1 , BL-T-B 2 and BL-C-B 2 extend through second isolation circuitry to the first BL-T conductive path, the first BL-C conductive path, the second BL-T conductive path and the second BL-C conductive path, respectively.

14. The method of claim 13 , wherein the second isolation circuitry includes a fifth transistor which gatedly connects BL-T-B 1 to the first BL-T conductive path, a sixth transistor which gatedly connects BL-C-B 1 to the first BL-C conductive path, a seventh transistor which gatedly connects BL-T-B 2 to the second BL-T conductive path, and an eighth transistor which gatedly connects BL-C-B 2 to the second BL-C conductive path.

15. The method of claim 14 , wherein the gates of the fifth, sixth, seventh and eighth transistors are coupled with a second bitline isolation driver.

16. The method of claim 12 wherein the first and second memory array decks A and B extend horizontally.

17. The method of claim 12 , wherein the gates of the first, second, third and fourth transistors are coupled with a first conductive line extending to the first bitline isolation driver.