Chip electronic component and electronic component mounting structure
A chip electronic component includes a stack, a first external electrode disposed at least on a first end surface and a first main surface of the stack, a second external electrode disposed at least on a second end surface and a first main surface of the stack, a first bump disposed at least on a portion of the first external electrode on the first main surface, and a second bump disposed at least on a portion of the second external electrode on the first main surface. The first bump and the second bump each have a porosity greater than or equal to about 5% and less than or equal to about 40%.
1. A chip electronic component, comprising:
a stack including a plurality of ceramic layers that are stacked and a plurality of inner electrodes stacked on the plurality of ceramic layers, the stack including:
a first main surface and a second main surface opposed each other in a thickness direction of the stack;
a first lateral surface and a second lateral surface opposed each other in a width direction of the stack perpendicular or substantially perpendicular to the thickness direction; and
a first end surface and a second end surface opposed each other in a length direction of the stack perpendicular to the thickness direction and the width direction;
a first external electrode disposed at least on the first end surface and the first main surface of the stack;
a second external electrode disposed at least on the second end surface and the first main surface of the stack;
a first bump electrically connected to the first external electrode; and
a second bump electrically connected to the second external electrode; wherein
the first bump is disposed at least on a portion of the first external electrode on the first main surface;
the second bump is disposed at least on a portion of the second external electrode on the first main surface;
the first bump includes a portion that is in contact with the first external electrode;
the second bump includes a portion that is in contact with the second external electrode; and
the first bump and the second bump each have a porosity greater than or equal to about 5% and less than or equal to about 40%.
2. The chip electronic component according to claim 1 , wherein the first bump and the second bump each have a thickness greater than or equal to about 30 μm and less than or equal to about 200 μm in the thickness direction.
3. The chip electronic component according to claim 1 , wherein the chip electronic component satisfies about 0.15≤e1/L≤about 0.4, where e1 is a total dimension of the first bump and the second bump in the length direction, and L is a dimension of the stack in the length direction.
4. The chip electronic component according to claim 1 , wherein
the first bump extends from a portion of the first external electrode to a portion of the first main surface of the stack when the chip electronic component is viewed along the thickness direction; and
the second bump extends from a portion of the second external electrode to a portion of the first main surface of the stack when the chip electronic component is viewed along the thickness direction.
5. The chip electronic component according to claim 1 , wherein
the first bump and the second bump each have a cuboid or substantially cuboid shape; and
the chip electronic component satisfies about 1.2≤f1/e1≤about 1.8, where f1 is a total dimension of the first bump and the second bump in the width direction, and e1 is a total dimension of the first bump and the second bump in the length direction.
6. The chip electronic component according to claim 5 , wherein the chip electronic component satisfies about 0.14≤f1*e1/L*W≤about 0.36, where L is a dimension of the stack in the length direction and W is a dimension of the stack in the width direction.
7. An electronic component mounting structure, comprising:
the chip electronic component according to claim 1 ; and
a mounting substrate including a substrate main body including a mounting surface, and a conductive land on the mounting surface; wherein
the first bump and the second bump, included in the chip electronic component, are mounted on the conductive land via solder with the mounting surface of the mounting substrate and the first main surface of the chip electronic component facing each other.
8. The electronic component mounting structure according to claim 7 , wherein
the solder is disposed at an interface between the first external electrode and the first bump and an interface between the second external electrode and the second bump.
9. The electronic component mounting structure according to claim 8 , wherein
the solder at the interface between the first external electrode and the first bump has a thickness greater than or equal to about 10 μm in the thickness direction at about one half a dimension, in the length direction, of a portion of the first external electrode on the first main surface of the stack; and
the solder at the interface between the second external electrode and the second bump has a thickness greater than or equal to about 10 μm in the thickness direction at about one half a dimension, in the length direction, of a portion of the second external electrode on the first main surface of the stack.
10. The electronic component mounting structure according to claim 7 , wherein the electronic component mounting structure satisfies Q>0, where Q is a distance in the thickness direction (i) from a plane coinciding with the first main surface of the stack to an edge of the solder on the first external electrode on the first end surface, the first lateral surface, and the second lateral surface, or (ii) from the plane coinciding with the first main surface of the stack to an edge of the solder on the second external electrode on the second end surface, the first lateral surface, and the second lateral surface of the stack.
11. The electronic component mounting structure according to claim 7 , wherein the electronic component mounting structure satisfies P>Q, where P is a distance in the thickness direction from the mounting surface of the mounting substrate to the first main surface of the stack included in the chip electronic component, and Q is a distance in the thickness direction (i) from a plane coinciding with the first main surface of the stack to an edge of the solder on the first external electrode on the first end surface, the first lateral surface, and the second lateral surface, or (ii) from the plane coinciding with the first main surface of the stack to an edge of the solder on the second external electrode on the second end surface, the first lateral surface, and the second lateral surface of the stack.
12. The electronic component mounting structure according to claim 7 , wherein the first bump and the second bump each have a thickness greater than or equal to about 30 μm and less than or equal to about 200 μm in the thickness direction.
13. The electronic component mounting structure according to claim 7 , wherein the chip electronic component satisfies about 0.15≤e1/L≤about 0.4, where e1 is a total dimension of the first bump and the second bump in the length direction, and L is a dimension of the stack in the length direction.
14. The electronic component mounting structure according to claim 7 , wherein
the first bump extends from a portion of the first external electrode to a portion of the first main surface of the stack when the chip electronic component is viewed along the thickness direction; and
the second bump extends from a portion of the second external electrode to a portion of the first main surface of the stack when the chip electronic component is viewed along the thickness direction.
15. The electronic component mounting structure according to claim 7 , wherein
the first bump and the second bump each have a cuboid or substantially cuboid shape; and
the chip electronic component satisfies about 1.2≤f1/e1≤about 1.8, where f1 is a total dimension of the first bump and the second bump in the width direction, and e1 is a total dimension of the first bump and the second bump in the length direction.
16. The electronic component mounting structure according to claim 15 , wherein the chip electronic component satisfies about 0.14≤f1*e1/L*W≤about 0.36, where L is a dimension of the stack in the length direction and W is a dimension of the stack in the width direction.
17. The chip electronic component according to claim 1 , wherein the first and second external electrodes include a baked layer.
18. The chip electronic component according to claim 17 , wherein the baked layer includes at least one metal selected from Cu, Ni, Ag, Pd, Ag—Pd alloy, or Au.
19. The chip electronic component according to claim 1 , wherein the first bump and the second bump each include an intermetallic compound as a main component.
20. The chip electronic component according to claim 19 , wherein the intermetallic compound includes a high melting point metal selected from Cu or Ni, and Sn as a low melting point metal.