Storage backed memory package save trigger
Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.
1. A memory package, the memory package comprising:
a volatile portion arranged to store data;
a non-volatile portion;
a first interface arranged to:
receive the data; and
receive a reset signal;
a second interface arranged to connect to a host; and
a processing device arranged to save the data stored in the volatile portion to the non-volatile portion in response to a determination that a dedicated save signal is inoperative.
2. The memory package of claim 1 , wherein the first interface comprises a version four double data rate (DDR4) random-access memory (RAM) interface.
3. The memory package of claim 2 , wherein the dedicated save signal is communicated by a pin corresponding to SAVE_n as defined in a Joint Electron Device Engineering Council (JEDEC) family of standards for version four double data rate (DDR4).
4. The memory package of claim 1 , wherein the second interface is a bus that operates in accordance with an Inter-Integrated Circuit (I2C) family of standards.
5. The memory package of claim 1 , wherein the processing device is further arranged to save the data stored in the volatile portion to the non-volatile portion in response to a self-refresh mode of the memory package being enabled at a time of the reset signal.
6. A method comprising:
receiving data via a first interface to store in a volatile portion of a memory package, the first interface being arranged to receive a reset signal, the memory package including a second interface arranged to connect a host to a processing device in the memory package;
determining whether a dedicated save signal is inoperative; and
saving the data stored in the volatile portion of the memory package to a non-volatile portion of the memory package in response to determining that the dedicated save signal is inoperative.
7. The method of claim 6 , wherein the first interface comprises a version four double data rate (DDR4) random-access memory (RAM) interface.
8. The method of claim 7 , wherein the dedicated save signal is communicated by a pin corresponding to SAVE_n as defined in a Joint Electron Device Engineering Council (JEDEC) family of standards for version four double data rate (DDR4).
9. The method of claim 6 , wherein the second interface is a bus that operates in accordance with an Inter-Integrated Circuit (I2C) family of standards.
10. The method of claim 6 , further comprising:
saving the data stored in the volatile portion to the non-volatile portion in response to a self-refresh mode of the memory package being enabled at a time of the reset signal.
11. At least one non-transitory machine readable medium including instructions, the instructions, when executed by processing circuitry of a memory package, cause the memory package to perform operations comprising:
receiving data via a first interface to store in a volatile portion of the memory package, the first interface being arranged to receive a reset signal, the memory package including a second interface arranged to connect a host to a processing device in the memory package;
determining whether a dedicated save signal is inoperative; and
saving the data stored in the volatile portion of the memory package to a non-volatile portion of the memory package in response to determining that the dedicated save signal is inoperative.
12. The at least one non-transitory machine readable medium of claim 11 , wherein the first interface comprises a version four double data rate (DDR4) random-access memory (RAM) interface.
13. The at least one non-transitory machine readable medium of claim 12 , wherein the dedicated save signal is communicated by a pin corresponding to SAVE_n as defined in a Joint Electron Device Engineering Council (JEDEC) family of standards for version four double data rate (DDR4).
14. The at least one non-transitory machine readable medium of claim 11 , wherein the second interface is a bus that operates in accordance with an Inter-Integrated Circuit (I2C) family of standards.
15. The at least one non-transitory machine readable medium of claim 11 , wherein the operations further comprise:
saving the data stored in the volatile portion to the non-volatile portion in response to a self-refresh mode of the memory package being enabled at a time of the reset signal.