Integrated component including a capacitor and discrete varistor

1. An integrated component comprising:

a multilayer capacitor having a top surface, a bottom surface opposite the top surface, a first end surface, a second end surface opposite the first end surface, a first side surface, and a second side surface opposite the first side surface, the multilayer capacitor comprising a first active termination, a second active termination, at least one ground termination, and a pair of capacitors connected in series between the first active termination and the second active termination, the multilayer capacitor further comprising:

a body comprising a plurality of dielectric layers;

a first plurality of electrode layers disposed within the body and connected with the first active termination;

a second plurality of electrode layers disposed within the body and connected with the second active termination; and

a third plurality of electrode layers connected with the at least one ground termination and capacitively coupled with each of the first plurality of electrode layers and second plurality of electrode layers to form a first capacitor of the pair of capacitors between the first plurality and third plurality of electrode layers and a second capacitor of the pair of capacitors between the second plurality and third plurality of electrode layers;

a discrete varistor comprising a first external varistor termination connected with the first active termination and a second external varistor termination connected with the second active termination of the multilayer capacitor, the discrete varistor having a clamping voltage within a range of about 15 volts to about 30 volts;

a first lead attached to the first active termination and the first external varistor termination;

a second lead attached to the second active termination and the second external varistor termination; and

a third lead attached to the at least one ground termination,

wherein at least one of the first plurality of electrode layers or the second plurality of electrode layers is connected with a respective one of the first active termination or the second active termination along the first side surface, the second side surface, and a respective one of the first end surface or the second end surface,

wherein the third plurality of electrode layers overlap with the first plurality of electrode layers along a first overlapping area, and

wherein the third plurality of electrode layers overlap with the second plurality of electrode layers along a second overlapping area that is different from the first overlapping area such that the first capacitor of the pair of capacitors has a first capacitance and the second capacitor of the pair of capacitors has a second capacitance that is different from the first capacitance.

2. The integrated component of claim 1 , wherein the third plurality of electrode layers are generally cross-shaped.

3. The integrated component of claim 1 , wherein the at least one ground termination comprises a first ground termination and a second ground termination.

4. The integrated component of claim 3 , wherein each of the third plurality of electrode layers comprises a pair of opposite edges, one of the opposite edges connected with the first ground termination and the other of the opposite edges connected with the second ground termination.

5. The integrated component of claim 3 , wherein the first ground termination is located opposite the second ground termination.

6. The integrated component of claim 1 , wherein the first, second, and third leads are respectively attached to the first active and first external varistor terminations, the second active and second external varistor terminations, and the at least one ground termination such that the first, second, and third leads extend perpendicular to the first plurality of electrode layers and the second plurality of electrode layers.

7. The integrated component of claim 1 , wherein at least one of the first capacitance or the second capacitance ranges from about 475 nF to about 3 μF.

8. The integrated component of claim 1 , wherein the discrete varistor is stacked relative to the multilayer capacitor.

9. The integrated component of claim 8 , further comprising an over-molded layer encapsulating the discrete varistor and the multilayer capacitor.

10. The integrated component of claim 1 , wherein a ratio of a thickness of the electrode stack-up to a thickness of the body is within a range of about 0.95 to about 0.97.

11. A method for forming an integrated component comprising:

providing a multilayer capacitor body including electrodes that form a first capacitor and a second capacitor, the multilayer capacitor body having a top surface, a bottom surface opposite the top surface, a first end surface, a second end surface opposite the first end surface, a first side surface, and a second side surface opposite the first side surface, wherein providing the multilayer capacitor body including electrodes forming the first capacitor and the second capacitor comprises:

forming a plurality of dielectric layers;

forming a first plurality of electrode layers disposed within the multilayer capacitor body; and

forming a second plurality of electrode layers disposed within the multilayer capacitor body;

forming a first active termination, a second active termination, and at least one ground termination external to the multilayer capacitor body, the first plurality of electrode layers connected with the first active termination and the second plurality of electrode layers connected with the second active termination such that the first capacitor and the second capacitor are connected in series between the first active termination and the second active termination;

stacking a discrete varistor with the multilayer capacitor body such that a first varistor termination of the discrete varistor is connected with the first active termination and a second varistor termination is connected with the second active termination; and

attaching a first lead to the first active termination and the first varistor termination, a second lead to the second active termination and the second varistor termination, and a third lead to the at least one ground termination,

wherein at least one of the first plurality of electrode layers or the second plurality of electrode layers is connected with a respective one of the first active termination or the second active termination along the first side surface, the second side surface, and a respective one of the first end surface or the second end surface,

wherein the first capacitor has a first capacitance and the second capacitor has a second capacitance,

wherein at least one of the first capacitance or the second capacitance ranges from about 475 nF to about 3 μF, and

wherein the plurality of dielectric layers, the first plurality of electrode layers, and the second plurality of electrode layers are stacked to form an electrode stack-up and a ratio of a thickness of the electrode stack-up to a thickness of the body is within a range of about 0.95 to about 0.97.

12. The method of claim 11 , further comprising:

forming a third plurality of electrode layers within the multilayer capacitor body connected with the at least one ground termination and capacitively coupled with each of the first plurality of electrode layers and the second plurality of electrode layers to form the first capacitor between the first plurality of electrode layers and the third plurality of electrode layers and the second capacitor between the second plurality of electrode layers and the third plurality of electrode layers.

13. The method of claim 12 , wherein forming the at least one ground termination comprises forming a first ground termination and a second ground termination.

14. The method of claim 12 , wherein the third plurality of electrode layers are generally cross-shaped.

15. The method of claim 12 , wherein each of the third plurality of electrode layers comprises a pair of opposite edges, one of the opposite edges connected with the first ground termination and the other of the opposite edges connected with the second ground termination.

16. The method of claim 12 , wherein:

the third plurality of electrode layers overlap with the first plurality of electrode layers along a first overlapping area; and

the third plurality of electrode layers overlap with the second plurality of electrode layers along a second overlapping area that is different from the first overlapping area such that the second capacitance is different from the first capacitance.

17. The method of claim 12 , wherein:

the third plurality of electrode layers overlap with the first plurality of electrode layers along a first overlapping area; and

the third plurality of electrode layers overlap with the second plurality of electrode layers along a second overlapping area that is approximately equal to the first overlapping area.

18. The method of claim 11 , wherein the first, second, and third leads are respectively attached to the first active and first varistor terminations, the second active and second varistor terminations, and the at least one ground termination such that each of the first, second, and third leads extends perpendicular to the first plurality of electrode layers and the second plurality of electrode layers.

19. The method of claim 11 , further comprising over-molding the discrete varistor and the multilayer capacitor body with an over-molded layer.

20. The method of claim 11 , wherein the discrete varistor has a clamping voltage within a range of about 15 volts to about 30 volts.

21. An integrated component comprising:

a multilayer capacitor comprising a body, a first active termination, a second active termination, at least one ground termination, and a pair of capacitors in the body, the pair of capacitors connected in series between the first active termination and the second active termination, the multilayer capacitor further comprising:

a first plurality of electrode layers disposed within the body and connected with the first active termination;

a second plurality of electrode layers disposed within the body and connected with the second active termination; and

a third plurality of electrode layers connected with the at least one ground termination and capacitively coupled with each of the first plurality of electrode layers and second plurality of electrode layers to form a first capacitor of the pair of capacitors between the first plurality and third plurality of electrode layers and a second capacitor of the pair of capacitors between the second plurality and third plurality of electrode layers; and

a discrete varistor comprising a first external varistor termination connected with the first active termination and a second external varistor termination connected with the second active termination of the multilayer capacitor,

wherein the discrete varistor is positioned on a top surface of the multilayer capacitor and is connected with the first and second active terminations at the top surface of the multilayer capacitor,

wherein at least one of the first active termination, the second active termination, or the at least one ground termination is exposed along a bottom surface of the multilayer capacitor, the bottom surface opposite the top surface,

wherein the discrete varistor has a clamping voltage within a range of about 15 volts to about 30 volts,

wherein the third plurality of electrode layers overlap with the first plurality of electrode layers along a first overlapping area, and

wherein the third plurality of electrode layers overlap with the second plurality of electrode layers along a second overlapping area that is different from the first overlapping area such that the first capacitor of the pair of capacitors has a first capacitance and the second capacitor of the pair of capacitors has a second capacitance that is different from the first capacitance.

22. The integrated component of claim 21 , wherein the integrated component is configured to be mounted on a mounting surface using grid array type mounting.

23. The integrated component of claim 21 , wherein at least one of the first capacitance or the second capacitance ranges from about 475 nF to about 3 μF, wherein the pair of capacitors of the multilayer capacitor further comprises a plurality of dielectric layers, wherein the plurality of dielectric layers and the plurality of electrode layers form an electrode stack-up, and wherein a ratio of a thickness of the electrode stack-up to a thickness of the body of the multilayer capacitor is within a range of about 0.95 to about 0.97.

24. The integrated component of claim 21 , wherein each second electrode layer includes a first electrode connected with the first active termination and a second electrode co-planar with the first electrode and connected with the second active termination, and wherein the plurality of first electrode layers are alternatingly stacked with the plurality of second electrode layers in the body of the multilayer capacitor.