Current flattening circuit for protection against power side channel attacks
Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.
1. A current flattening circuit for an electrical load, comprising:
one or more pass-gate transistor arranged in series with the load and configured with a fixed gate bias voltage;
a differential high pass filter coupled across the one or more pass-gate transistor;
a controlled current source configured to respond to an output of the differential high pass filter to generate a proportional shunt current for the load.
2. The current flattening circuit of claim 1 , wherein the controlled current source is configured as a feedback current regulator.
3. The current flattening circuit of claim 1 , the shunt current configured to be directed to circuit ground.
4. The current flattening circuit of claim 1 , the differential high pass filter comprising a mirrored pair of cells, each cell comprising a PMOS transistor stacked with an NMOS transistor.
5. The current flattening circuit of claim 4 , further comprising a differential amplifier interposed between the differential high pass filter and the controlled current source.
6. The current flattening circuit of claim 5 , further comprising a capacitor coupled to receive an output of the differential amplifier.
7. The current flattening circuit of claim 1 , configured such that a sensed voltage across the one or more pass-gate transistor controls an amount of the shunt current.
8. A circuit comprising:
a regulated transistor interposed between a power supply and a load;
a differential high pass filter coupled across the load current sensor, the differential high pass filter having a gain;
a differential amplifier coupled to outputs of the differential high pass filter; and
the differential amplifier coupled to control a current source shunting the load.
9. The circuit of claim 8 wherein the regulated transistor is a PMOS transistor configured with a fixed gate bias voltage.
10. The circuit of claim 8 further comprising a capacitor connected at a node connecting an output of the differential amplifier to a control input of the current source.
11. The circuit of claim 8 , wherein the current source comprises a feedback current regulator.
12. The circuit of claim 8 , the current source configured to shunt current to circuit ground from a power supply input for the load.
13. The circuit of claim 8 , the differential high pass filter comprising a mirrored pair of cells, each cell comprising a PMOS transistor stacked with an NMOS transistor.
14. The circuit of claim 8 , configured such that a sensed voltage across the load current sensor controls an amount of current flowing through the current source.
15. A process for flattening variations in a supply voltage applied to a load, the proccess comprising:
applying a constant gate bias to a transistor interposed between the supply voltage and the load;
high pass filtering a voltage generated across the transistor to generate high-passed filtered voltage;
applying the high-passed filtered voltage to a differential amplifier to generate a control voltage; and
controlling a current source shunting the load with the control voltage.
16. The process of claim 15 , further comprising:
amplifying the voltage across the transistor with a high pass filter utilized for the high pass filtering.
17. The process of claim 15 , wherein the high-pass filtering is performed with a mirrored pair of cells, each cell comprising a PMOS transistor stacked with an NMOS transistor.