IP Library Granted Patent US 11,416,338
Granted Patent B2
US 11,416,338 · App. 16/857,475 · Granted Aug 16, 2022

Resiliency scheme to enhance storage performance

Inventors: Hari Kannan (Sunnyvale, CA); Nenad Miladinovic (Campbell, CA)
Assignee: Pure Storage, Inc.
G06F11/108G06F11/106G06F11/1096G06F11/2069G06F11/2094G06F12/0246G06F2211/109G06F2212/7211
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,416,338
App. No.
16/857,475
Granted
Aug 16, 2022
Kind
B2
Abstract

A storage system has a resiliency scheme to enhance storage system performance. The storage system composes a RAID stripe. The storage system mixes an ordering of portions of the RAID stripe, based on reliability differences across portions of the solid-state memory. The storage system writes the mixed ordering RAID stripe across the solid-state memory.

Claims (58)

1. A method, comprising:

composing a RAID stripe of data to be written across solid-state memory of a storage system;

mixing an ordering of portions of the RAID stripe of data, based on reliability differences across portions of the solid-state memory;

selecting an error correction code (ECC) scheme based on the reliability differences across the portions of the solid-state memory, for the RAID stripe of data; and

writing the mixed ordering RAID stripe of data across the solid-state memory.

2. The method of claim 1 , wherein:

the reliability differences comprise reliability differences among pages of an atomic write page group of the solid-state memory;

the mixed ordering of portions of the RAID stripe comprises a first RAID stripe with a first mixed ordering into pages of a first atomic write page group in the solid-state memory; and

the storage system is further to write a second, differing mixed ordering of portions of a second RAID stripe into pages of a second atomic write page group in the solid-state memory.

3. The method of claim 1 , wherein:

the reliability differences comprise reliability differences among pages in an atomic write page group of the solid-state memory; and

the mixed ordering of portions of the RAID stripe comprises a first mixed ordering of a first portion of the RAID stripe across a first type of solid-state memory and a second, differing mixed ordering of a second portion of the RAID stripe of data across a second type of solid-state memory.

4. The method of claim 1 , further comprising:

using an identifier of a storage device of the storage system as a seed for a function that determines the mixed ordering.

5. The method of claim 1 , further comprising:

reading the mixed ordering RAID stripe of data from the solid-state memory; and

rearranging the ordering of the portions of the mixed ordering RAID stripe to reconstitute the RAID stripe of data.

6. The method of claim 1 , further comprising:

scrubbing the solid-state memory, through wear monitoring the solid-state memory at varied address intervals or varied address offsets, and rewriting data from worn regions of solid-state memory to further regions of solid-state memory using mixed ordering of portions of the rewritten data.

7. A tangible, non-transient, computer readable media having instructions thereon for one or more processors to perform a method, comprising:

composing a RAID stripe of data to be written across solid-state memory of a storage system;

mixing an ordering of portions of the RAID stripe of data, based on reliability differences across portions of the solid-state memory, the mixing using an identifier of a storage device of the storage system as a seed for a function that determines the mixed ordering; and

writing the mixed ordering RAID stripe of data across the solid-state memory.

8. The computer readable media of claim 7 , wherein:

the reliability differences comprise reliability differences among pages of an atomic write page group of the solid-state memory;

the mixed ordering of portions of the RAID stripe comprises a first RAID stripe with a first mixed ordering into pages of a first atomic write page group in the solid-state memory; and

the storage system is further to write a second, differing mixed ordering of portions of a second RAID stripe into pages of a second atomic write page group in the solid-state memory.

9. The computer readable media of claim 7 , wherein:

the reliability differences comprise reliability differences among pages in an atomic write page group of the solid-state memory; and

the mixed ordering of portions of the RAID stripe comprises a first mixed ordering of a first portion of the RAID stripe across a first type of solid-state memory and a second, differing mixed ordering of a second portion of the RAID stripe of data across a second type of solid-state memory.

10. The computer readable media of claim 7 , wherein the method further comprises:

reading the mixed ordering RAID stripe of data from the solid-state memory; and

rearranging the ordering of the portions of the mixed ordering RAID stripe to reconstitute the RAID stripe of data.

11. The computer readable media of claim 7 , wherein the method further comprises:

selecting an error correction code (ECC) scheme based on the reliability differences across the portions of the solid-state memory, for the RAID stripe of data.

12. The computer readable media of claim 7 , wherein the method further comprises:

scrubbing the solid-state memory, through wear monitoring the solid-state memory at varied address intervals or varied address offsets, and rewriting data from worn regions of solid-state memory to further regions of solid-state memory using mixed ordering of portions of the rewritten data.

13. A storage system, comprising:

solid-state memory; and

a processing device to:

compose a RAID stripe of data to be written across solid-state memory of the storage system;

mix an ordering of portions of the RAID stripe of data, based on reliability differences across portions of the solid-state memory;

select an error correction code (ECC) scheme based on the reliability differences across the portions of the solid-state memory, for the RAID stripe of data; and

write the mixed ordering RAID stripe of data across the solid-state memory.

14. The storage system of claim 13 , wherein:

the reliability differences comprise reliability differences among pages of an atomic write page group of the solid-state memory;

the mixed ordering of portions of the RAID stripe comprises a first RAID stripe with a first mixed ordering into pages of a first atomic write page group in the solid-state memory; and

the processing device is further to write a second, differing mixed ordering of portions of a second RAID stripe into pages of a second atomic write page group in the solid-state memory.

15. The storage system of claim 13 , wherein:

the reliability differences comprise reliability differences among pages in an atomic write page group of the solid-state memory; and

the mixed ordering of portions of the RAID stripe comprises a first mixed ordering of a first portion of the RAID stripe across a first type of solid-state memory and a second, differing mixed ordering of a second portion of the RAID stripe of data across a second type of solid-state memory.

16. The storage system of claim 13 , wherein the processing device is further to:

use an identifier of a storage device of the storage system as a seed for a function that determines the mixed ordering.

17. The storage system of claim 13 , wherein the processing device is further to:

read the mixed ordering RAID stripe of data from the solid-state memory; and

rearrange the ordering of the portions of the mixed ordering RAID stripe to reconstitute the RAID stripe of data.

18. The storage system of claim 13 , wherein the processing device is further to:

scrub the solid-state memory, through wear monitoring the solid-state memory at varied address intervals or varied address offsets, and rewriting data from worn regions of solid-state memory to further regions of solid-state memory using mixed ordering of portions of the rewritten data.

Assignments (3)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS Recorded Jun 11, 2025
From: BARCLAYS BANK PLC, AS ADMINISTRATIVE AGENT
To: PURE STORAGE, INC.
Reel/Frame 071558/0523 →
SECURITY INTEREST Recorded Aug 26, 2020
From: PURE STORAGE, INC.
To: BARCLAYS BANK PLC AS ADMINISTRATIVE AGENT
Reel/Frame 053867/0581 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2020
From: KANNAN, HARI; MILADINOVIC, NENAD
To: PURE STORAGE, INC.
Reel/Frame 052486/0391 →
Continuity (1)
Related Publication 20210334157A1 · Oct 28, 2021
Cited By (1)
US 12,235,743