Clock synchronization

1. A method for determining delay between clocks of a first coherent transceiver and a second coherent transceiver in a coherent optical system, the method comprising:

in response to a trigger event, buffering digital signal processor (DSP) symbol information in a symbol capture buffer of the first coherent transceiver; wherein the amount of DSP symbol information buffered corresponds to the amount of symbols captured during a buffer storage interval;

extracting a synchronization packet from the symbol capture buffer; wherein the symbol capture buffer is located within a coherent optical DSP of the first coherent transceiver; and

calculating a total Egress TX delay by summing an Egress system-side delay, a Fixed Delay D1, Egress line-side delay, and Fixed Delay D2.

2. The method of claim 1 wherein the buffer storage time is approximately 2 us.

3. The method of claim 1 further comprising using the synchronization packet to set a clock on a peer.

4. The method of claim 1 wherein the synchronization packet has a timestamp.

5. The method of claim 4 wherein the timestamp is used to determine delay in a transmission line.

6. The method of claim 5 wherein the buffer storage interval depends on a number of symbols to be collected in the capture buffer.

7. A system for determining delay between clocks of a first coherent transceiver and a second coherent transceiver in a coherent optical system, the system comprising:

a symbol capture buffer; wherein the symbol capture buffer is enabled to storage symbols received during a buffer storage interval; wherein the symbol capture buffer is located within a digital signal processor (DSP) of a first coherent transceiver; and

logic; wherein the logic is enabled to extract a synchronization packet from the symbol capture buffer and calculate a total Egress TX delay by summing an Egress system-side delay, a Fixed Delay D1, Egress line-side delay, and Fixed Delay D2.

8. The system of claim 7 wherein the buffer storage interval is approximately 2 us.

9. The system of claim 7 wherein the logic is further enabled to use the synchronization packet to set a clock on a peer.

10. The system of claim 7 wherein the synchronization packet has a timestamp.

11. The system of claim 10 wherein the timestamp is used to determine delay in a transmission line.

12. The system of claim 11 wherein the buffer storage interval depends on a number of symbols to be collected in the capture buffer.

13. The system of claim 12 wherein the number of symbols to be collected is determined by an amount of symbols needed to be captured to find the synchronization packet.

14. The method of claim 6 wherein the number of symbols to be collected is determined by an amount of symbols needed to be captured to find the synchronization packet.

15. A coherent optical system apparatus comprising:

a symbol capture buffer; wherein the symbol capture buffer is enabled to storage symbols received during a buffer storage interval; wherein the symbol capture buffer is located within a digital signal processor (DSP) of a first coherent transceiver; and

logic; wherein the logic is enabled to extract a synchronization packet from the symbol capture buffer of the DSP and calculate a total Egress TX delay by summing an Egress system-side delay, a Fixed Delay D1, Egress line-side delay, and Fixed Delay D2.

16. The apparatus of claim 15 wherein the buffer storage interval depends on a number of symbols to be collected in the capture buffer.

17. The apparatus of claim 16 wherein the number of symbols to be collected is determined by an amount of symbols needed to be captured to find the synchronization packet.

18. The apparatus of claim 17 wherein the logic is further enabled to use the synchronization packet to set a clock on a peer.

19. The apparatus of claim 18 wherein the synchronization packet has a timestamp.

20. The apparatus of claim 19 wherein the timestamp is used to determine delay in a transmission line.