Systems and methods for performing quantum evolution in quantum computation
A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
1. A method of operation of a hybrid computer, the hybrid computer comprising an analog processor and a digital processor, the method performed by the digital processor, the method comprising:
determining, for a first interval of a normalized evolution coefficient, a first evolution schedule and a second evolution schedule, each of the first evolution schedule and the second evolution schedule defining a respective time dependence of the normalized evolution coefficient, the first interval bounded by a first value of the normalized evolution coefficient and a second value of the normalized evolution coefficient;
programming the analog processor using the first evolution schedule;
causing the analog processor to evolve in accordance with the first evolution schedule in a direction of increasing normalized evolution coefficient from the first value of the normalized evolution coefficient to the second value of the normalized evolution coefficient;
causing the analog processor to evolve in accordance with the first evolution schedule in a direction of decreasing normalized evolution coefficient from the second value of the normalized evolution coefficient to the first value of the normalized evolution coefficient;
programming the analog processor using the second evolution schedule;
causing the analog processor to evolve in accordance with the second evolution schedule in the direction of increasing normalized evolution coefficient from the first value of the normalized evolution coefficient to the second value of the normalized evolution coefficient;
causing the analog processor to evolve in accordance with the second evolution schedule in the direction of decreasing normalized evolution coefficient from the second value of the normalized evolution coefficient to the first value of the normalized evolution coefficient;
determining whether an exit condition has been met, and upon determining an exit condition has been met:
determining, for a second interval of the normalized evolution coefficient, a third evolution schedule, the third evolution schedule defining a time dependence of the normalized evolution coefficient, the second interval bounded by the second value of the normalized evolution coefficient and a third value of the normalized evolution coefficient; and
programming the analog processor using the third evolution schedule; and
causing the analog processor to evolve in accordance with the third evolution schedule in the direction of increasing normalized evolution coefficient from the second value of the normalized evolution coefficient to the third value of the normalized evolution coefficient.
2. The method of claim 1 , wherein the determining whether an exit condition has been met includes determining the analog processor has been evolved in accordance with a defined number N of evolution schedules for the first interval, the defined number N greater than one.
3. The method of claim 1 , further comprising, after causing the analog processor to evolve in accordance with the second evolution schedule in the direction of increasing normalized evolution coefficient from the first value of the normalized evolution coefficient to the second value of the normalized evolution coefficient, reading out a spin configuration of the analog processor.
4. The method of claim 3 , wherein determining whether an exit condition has been met includes determining whether an
exit condition based at least in part on the spin configuration of the analog processor has been met.
5. The method of claim 1 , wherein programming the analog processor using the first evolution schedule includes programming a quantum processor using the first evolution schedule.
6. The method of claim 5 , wherein the programming a quantum processor using the first evolution schedule includes programming a quantum annealer using the first evolution schedule, the first evolution schedule which includes an annealing schedule.
7. The method of claim 5 , wherein the programming a quantum processor using the first evolution schedule includes programming a quantum processor using the first evolution schedule, the quantum processor including a plurality of superconducting qubits.
8. The method of claim 7 , wherein the programming a quantum processor using the first evolution schedule, the quantum processor including a plurality of superconducting qubits includes programming a quantum processor using the first evolution schedule, the quantum processor including a plurality of superconducting flux qubits, and wherein the normalized evolution coefficient is representative of a normalized flux applied to a compound Josephson junction or a normalized persistent current of a flux qubit of the plurality of superconducting qubits.
9. The method of claim 1 , wherein the causing the analog processor to evolve in accordance with the first evolution schedule in a direction of increasing normalized evolution coefficient from the first value of the normalized evolution coefficient to the second value of the normalized evolution coefficient includes causing the analog processor to evolve in accordance with the first evolution schedule in a direction of increasing normalized evolution coefficient, the normalized evolution coefficient changing monotonically from the first value of the normalized evolution coefficient to the second value of the normalized evolution coefficient.
10. A hybrid computer for solving a computational problem, the hybrid computer comprising:
an analog processor;
a digital processor; and
at least one nontransitory processor-readable medium communicatively coupleable to the digital processor, the nontransitory processor-readable medium which stores at least one of processor-executable instructions or data which, when executed by the digital processor, cause the digital processor to:
determine, for a first interval of a normalized evolution coefficient, a first evolution schedule and a second evolution schedule, each of the first and the second evolution schedule defining a respective time dependence of the normalized evolution coefficient, the first interval bounded by a first value of the normalized evolution coefficient and a second value of the normalized evolution coefficient;
program the analog processor using the first evolution schedule;
cause the analog processor to evolve in accordance with the first evolution schedule in a direction of increasing normalized evolution coefficient from the first value of the normalized evolution coefficient to the second value of the normalized evolution coefficient;
cause the analog processor to evolve in accordance with the first evolution schedule in a direction of decreasing normalized evolution coefficient from the second value of the normalized evolution coefficient to the first value of the normalized evolution coefficient;
program the analog processor using the second evolution schedule;
cause the analog processor to evolve in accordance with the second evolution schedule in the direction of increasing normalized evolution coefficient from the first value of the normalized evolution coefficient to the second value of the normalized evolution coefficient;
cause the analog processor to evolve in accordance with the second evolution schedule in the direction of decreasing normalized evolution coefficient from the second value of the normalized evolution coefficient to the first value of the normalized evolution coefficient; and
determine whether an exit condition has been met, and upon a determination that an exit condition has been met:
determine, for a second interval of the normalized evolution coefficient, a third evolution schedule, the third evolution schedule defining a time dependence of the normalized evolution coefficient, the second interval bounded by the second value of the normalized evolution coefficient and a third value of the normalized evolution coefficient;
program the analog processor using the third evolution schedule; and
cause the analog processor to evolve in accordance with the third evolution schedule in a direction of increasing normalized evolution coefficient from the second value of the normalized evolution coefficient to the third value of the normalized evolution coefficient.
11. The hybrid computer of claim 10 , wherein to determine an exit condition has been met the at least one of processor-executable instructions or data which, when executed by the digital processor, cause the digital processor to determine whether the analog processor has been evolved in accordance with a defined number N of evolution schedules for the first interval, the defined number N greater than one.
12. The hybrid computer of claim 10 , the at least one of processor-executable instructions or data which, when executed by the digital processor, after causing the analog processor to evolve in accordance with the second evolution schedule in a direction of increasing normalized evolution coefficient from the first value of the normalized evolution coefficient to the second value of the normalized evolution coefficient, further cause the digital processor to read out a spin configuration of the analog processor.
13. The hybrid computer of claim 12 ,
wherein the exit condition is based at least in part on the spin configuration of the analog processor.
14. The hybrid computer of claim 10 , wherein the analog processor includes a quantum processor.
15. The hybrid computer of claim 14 , wherein the quantum processor includes a quantum annealer, and each of the first and the second evolution schedule includes a respective annealing schedule.
16. The hybrid computer of claim 14 , wherein the quantum processor includes a plurality of superconducting qubits.
17. The hybrid computer of claim 10 , wherein the respective time dependence of the normalized evolution coefficient for each of the first and the second evolution schedule is monotonic.
18. A method of operation of a hybrid computer, the hybrid computer comprising an analog processor and a digital processor, the method performed by the digital processor, the method comprising:
determining a plurality of evolution schedules for two or more intervals i of a normalized evolution coefficient s;
iteratively repeating for each interval i of the normalized evolution coefficient s:
iteratively repeating until an exit condition has been met:
programming the analog processor using an evolution schedule of the plurality of evolution schedules;
evolving the analog processor in a direction of increasing normalized evolution coefficient from a value s i of the normalized evolution coefficient to a value s i+1 of the normalized evolution coefficient; and
evolving the analog processor in a direction of decreasing normalized evolution coefficient from the value s i+1 of the normalized evolution coefficient to a value s i of the normalized evolution coefficient.