Slice memory control
Embodiments of the present disclosure relate to managing communications between slices on a storage device engine. Shared slice memory of a storage device engine is provisioned for use by each slice of the storage device engine. The shared slice memory is a portion of total storage device engine memory. Each slice's access to the shared memory portion is controlled.
1. A method comprising:
provisioning shared slice memory for a director board of a pair of director boards corresponding to a storage array's storage device engine for use by each slice of the director board, wherein the shared slice memory is a portion of total director board memory that includes dynamic random-access memory (DRAM) and wherein the storage device engine is housed in a shelf that interfaces with a cabinet and/or rack of a storage array;
determining task types related to each activity performed by each worker thread of each slice, wherein determining the task types includes identifying a source identification in each slice-issued shared memory access request;
correlating each slice's shared memory access requests with each task type; and
controlling each slice's access to the shared memory portion based on the correlation.
2. The method of claim 1 further comprising provisioning local slice memory portions of the total director board memory for each slice.
3. The method of claim 2 further comprising assigning each local slice memory portion to a distinct slice of the director board.
4. The method of claim 1 further comprising establishing one or more shared queues from the shared slice memory.
5. The method of claim 4 , further comprising configuring each shared queue to buffer memory access requests from each slice.
6. The method of claim 4 further comprising associating each shared queue with one or more operation types.
7. The method of claim 4 further comprising configuring a shared memory index for each shared queue.
8. The method of claim 7 further comprising establishing an index element in the shared memory index to reference a buffer location corresponding to the shared queue for which the shared memory index is established.
9. The method of claim 8 further comprising:
monitoring a state of each shared memory index; and
directing each memory access request to a shared queue based on one or more of the states of each shared memory index and an operation type of the memory access request;
buffering each memory access request in the shared queue to which each memory access request is directed.
10. The method of claim 9 further comprising:
updating the states of each shared memory index to which each memory access request is directed; and
providing the states of each shared memory index to each slice.
11. An apparatus comprising a memory and at least one processor configured to:
provision shared slice memory for a director board of a pair of director boards corresponding to a storage array's storage device engine for use by each slice of the director board, wherein the shared slice memory is a portion of total director board memory that includes dynamic random-access memory (DRAM) and wherein the storage device engine is housed in a shelf that interfaces with a cabinet and/or rack of a storage array;
determine task types related to each activity performed by each worker thread of each slice, wherein determining the task types includes identifying a source identification in each slice-issued shared memory access request;
correlate each slice's shared memory access requests with each task type; and
control each slice's access to the shared memory portion based on the correlation.
12. The apparatus of claim 11 further configured to provision local slice memory portions of the total director board memory for each slice.
13. The apparatus of claim 12 further configured to assign each local slice memory portion to a distinct slice of the director board.
14. The apparatus of claim 11 further configured to establish one or more shared queues from the shared slice memory.
15. The apparatus of claim 14 , further configured to configure each shared queue to buffer memory access requests from each slice.
16. The apparatus of claim 14 further configured to associate each shared queue with one or more operation types.
17. The apparatus of claim 14 further configured to configure a shared memory index for each shared queue.
18. The apparatus of claim 17 further configured to establish an index element in the shared memory index to reference a buffer location corresponding to the shared queue for which the shared memory index is established.
19. The apparatus of claim 18 further configured to:
monitor a state of each shared memory index; and
direct each memory access request to a shared queue based on one or more of the states of each shared memory index and an operation type of the memory access request;
buffer each memory access request in the shared queue to which each memory access request is directed.
20. The apparatus of claim 19 further configured to:
update the states of each shared memory index to which each memory access request is directed; and
provide the states of each shared memory index to each slice.