PCIe link management without sideband signals
A system for controlling data communications, comprising an enclosure management processor configured to generate a peripheral component interconnect express reset command and a chip reset command. A re-timer configured to receive the peripheral component interconnect express reset command and the chip reset command and to control a communications port in response to the peripheral component interconnect express reset command and the chip reset command. The communications port configured to reset in response to a control signal from the re-timer.
1. A system for controlling data communications, comprising:
an enclosure management processor configured to generate a port reset command, a peripheral component interconnect express reset command and a chip reset command;
a re-timer coupled to the enclosure management processor by a two wire interface bus and a separate port reset pin connection and configured to receive the peripheral component interconnect express reset command and the chip reset command and to control a communications port in response to the peripheral component interconnect express reset command and the chip reset command; and
the communications port configured to reset in response to a control signal from the re-timer, wherein the enclosure management processor further comprises a switch state machine for a plurality of switch states, wherein the switch state machine receives link status data and generates the port reset command in response to a link status of no link, the peripheral component interconnect express reset command and the chip reset command as a function of the switch state machine output.
2. The system of claim 1 wherein the enclosure management processor further comprises a re-timer state machine for a plurality of re-timer states, wherein the re-timer state machine receives link status data and generates the peripheral component interconnect express reset command in response to a link status of no link and the chip reset command as a function of the re-timer state machine output.
3. The system of claim 1 wherein the communications port is configured to reset in response to a port reset signal and further comprising a chip reset pin coupled to a host CPU.
4. The system of claim 1 further comprising a second enclosure management processor coupled to a mini-serial attached SCSI HD cable port and a plurality of endpoints coupled to a switch and configured to generate a downstream peripheral component interconnect express reset command and a downstream chip reset command to perform communications with the plurality of endpoints.
5. The system of claim 1 further comprising a second re-timer configured to receive a second peripheral component interconnect express reset command and a second chip reset command and to control a second communications port in response to the second peripheral component interconnect express reset command and the second chip reset command.
6. The system of claim 1 further comprising a second communications port configured to reset in response to a control signal from a second re-timer.
7. The system of claim 1 wherein the switch state machine comprises a plurality states for a first link width including a width of zero and a width of greater than zero a plurality of states for a second link width including a width of zero and a width of greater than zero.
8. The system of claim 1 wherein the switch state machine comprises a plurality states for a first link width of zero state and a plurality of states for a second link width of at least one lane to at least 16 lanes.
9. The system of claim 1 wherein the switch state machine comprises a detect state for a first link width a detect state and for a second link width that is different from the first link width.
10. A system for controlling data communications, comprising:
an enclosure management processor configured to generate a port reset command, a peripheral component interconnect express reset command and a chip reset command;
a re-timer coupled to the enclosure management processor by a two wire interface bus and a separate port reset pin connection and configured to receive the peripheral component interconnect express reset command and the chip reset command and to control a communications port in response to the peripheral component interconnect express reset command and the chip reset command; and
the communications port configured to reset in response to a control signal from the re-timer, wherein the enclosure management processor further comprises a re-timer state machine for a plurality of re-timer states, wherein the re-timer state machine receives link status data and generates the peripheral component interconnect express reset command in response to a link status of no link and the chip reset command as a function of the re-timer state machine output.
11. The system of claim 10 wherein the communications port is configured to reset in response to a port reset signal and further comprising a chip reset pin coupled to a host CPU.
12. The system of claim 10 further comprising a second enclosure management processor coupled to a mini-serial attached SCSI HD cable port and a plurality of endpoints coupled to a switch and configured to generate a downstream peripheral component interconnect express reset command and a downstream chip reset command to facilitate communications with the plurality of endpoints.
13. The system of claim 10 further comprising a second re-timer configured to receive a second peripheral component interconnect express reset command and a second chip reset command and to control a second communications port in response to the second peripheral component interconnect express reset command and the second chip reset command.
14. The system of claim 10 further comprising a second communications port configured to reset in response to a control signal from a second re-timer, and the re-timer comprises a chip reset pin coupled to the enclosure management processor by the two wire interface bus.
15. The system of claim 10 wherein the switch state machine comprises a plurality states for a first link width including a width of zero and a width of greater than zero a plurality of states for a second link width including a width of zero and a width of greater than zero.
16. The system of claim 10 wherein the switch state machine comprises a plurality states for a first link width of zero state and a plurality of states for a second link width of at least one lane to at least 16 lanes.
17. The system of claim 10 wherein the switch state machine comprises a detect state for a first link width a detect state and for a second link width that is different from the first link width.
18. A system for controlling data communications, comprising:
an enclosure management processor configured to generate a port reset command, a peripheral component interconnect express reset command and a chip reset command;
a re-timer coupled to the enclosure management processor by a two wire interface bus and a separate port reset pin connection and configured to receive the peripheral component interconnect express reset command and the chip reset command and to control a communications port in response to the peripheral component interconnect express reset command and the chip reset command; and
the communications port configured to reset in response to a control signal from the re-timer, wherein the enclosure management processor further comprises a switch state machine for a plurality of switch states, wherein the switch state machine receives link status data and generates the port reset command in response to a link status of no link, the peripheral component interconnect express reset command and the chip reset command as a function of the switch state machine output, and wherein the enclosure management processor further comprises a re-timer state machine for a plurality of re-timer states, wherein the re-timer state machine receives link status data and generates the peripheral component interconnect express reset command in response to a link status of no link and the chip reset command as a function of the re-timer state machine output.
19. The system of claim 18 wherein the communications port is configured to reset in response to a port reset signal and further comprising a chip reset pin coupled to a host CPU.
20. The system of claim 18 further comprising a second enclosure management processor coupled to a mini-serial attached SCSI HD cable port and a plurality of endpoints coupled to a switch and configured to generate a downstream peripheral component interconnect express reset command and a downstream chip reset command to facilitate communications with the plurality of endpoints.