Semiconductor device
A semiconductor device includes a substrate having a first surface and a second surface opposite to each other, and having an active region located on the first surface and defined by a first isolation region; a plurality of active fins arranged on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the plurality of active fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the buried conductive wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.
1. A semiconductor device comprising:
a substrate comprising a first surface and a second surface opposite to each other, and comprising an active region on the first surface and defined by a first isolation region;
a plurality of active fins arranged on the active region, wherein the plurality of active fins extend in a first direction and are defined by a second isolation region having a second depth smaller than a first depth of the first isolation region, wherein the plurality of fins are spaced apart in a second direction that is different from the first direction;
a buried conductive wiring in a trench adjacent to the plurality of active fins, and extending in the first direction, wherein the trench comprises a trench depth extending along a vertical direction that is perpendicular to the first and second directions, and wherein the trench depth is less than the first depth of the first isolation region and greater than the second depth of the second isolation region;
a filling insulation portion in the trench, and comprising the buried conductive wiring therein;
an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring;
a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and
a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.
2. The semiconductor device according to claim 1 , wherein a portion of the conductive through structure contacts the filling insulation portion.
3. The semiconductor device according to claim 2 , wherein an upper end of the conductive through structure extends towards the first surface beyond a bottom surface of the buried conductive wiring.
4. The semiconductor device according to claim 1 , wherein an upper end of the conductive through structure is confined below an upper surface of the active region.
5. The semiconductor device according to claim 1 , wherein the conductive through structure comprises a conductive material, and a dielectric liner between the conductive material and the substrate.
6. The semiconductor device according to claim 1 , wherein the trench is located in the active region between ones of the plurality of active fins.
7. The semiconductor device according to claim 1 , wherein the trench has a first width adjacent to a lower end of the plurality of active fins that is greater than a second width thereof adjacent to the buried conductive wiring.
8. The semiconductor device according to claim 1 , wherein the buried conductive wiring has an upper surface that is between an upper surface of the active region and respective upper ends of the active fins.
9. The semiconductor device according to claim 1 , wherein the buried conductive wiring comprises a conductive material, and a conductive barrier on a side surface and a lower surface of the conductive material.
10. The semiconductor device according to claim 9 , wherein the buried conductive wiring further comprises a dielectric barrier between the conductive barrier and the filling insulation portion.
11. A semiconductor device comprising:
a substrate comprising an upper surface and a rear surface;
a trench in the substrate having a first width and a depth and extending in a horizontal direction;
a buried conductive wiring in the trench, extending in the horizontal direction, and having a second width, narrower than the first width;
a filling insulation portion in the trench, and comprising the buried conductive wiring therein;
a device isolation layer in the substrate and defining an active region, wherein the device isolation layer has first and second depths along the vertical direction, and the depth of the trench is greater than the first depth and less than the second depth;
an interlayer insulation layer on the device isolation layer, the active region, and the buried conductive wiring;
a contact structure penetrating the interlayer insulation layer and contacting the buried conductive wiring;
a conductive through structure extending through the substrate from the rear surface to the trench and comprising an end portion adjacent the trench and contacting the buried conductive wiring; and
a backside wiring portion on the rear surface of the substrate and electrically connected to the conductive through structure.
12. The semiconductor device according to claim 11 , further comprising a source/drain region in the active region,
wherein the contact structure penetrates the interlayer insulation layer and contacts the source/drain region.
13. The semiconductor device according to claim 11 , wherein the end portion of the conductive through structure partially contacts the filling insulation portion and extends toward the upper surface beyond a bottom surface of the buried conductive wiring.
14. A semiconductor device comprising:
a substrate comprising an upper surface comprising an active region;
a plurality of active fins on the active region and extending in one direction;
a buried conductive wiring in a trench adjacent to the plurality of active fins, and extending in the one direction;
a dielectric barrier between an inner side wall of the trench and a side surface of the buried conductive wiring;
an interlayer insulation layer on the upper surface of the substrate, and on the buried conductive wiring;
a contact structure penetrating the interlayer insulation layer, and contacting buried conductive wiring;
a through-hole penetrating the substrate from a rear surface of the substrate, and comprising a bottom surface that exposes a lower surface of the buried conductive wiring and a portion of the substrate;
a conductive through structure comprising a dielectric liner on the portion of the substrate and on an inner side wall, and a conductive material in the through-hole and contacting the lower surface of the buried conductive wiring; and
a backside wiring portion on the rear surface of the substrate and electrically connected to the conductive through structure.
15. The semiconductor device according to claim 14 , wherein an upper end of the conductive through structure extends toward the upper surface of the substrate beyond the lower surface of the buried conductive wiring.
16. The semiconductor device according to claim 14 , wherein the buried conductive wiring has an upper surface that is between an upper surface of the active region and respective upper ends of the active fins.
17. The semiconductor device according to claim 14 , wherein a portion of the side surface of the buried conductive wiring is exposed by the through-hole.
18. The semiconductor device according to claim 17 , wherein the dielectric barrier extends to the side surface of the buried conductive wiring exposed by the through-hole, and the dielectric liner is on a portion of the dielectric barrier.
19. The semiconductor device according to claim 14 , wherein a width of the trench is wider than a width of the buried conductive wiring, and
the interlayer insulation layer comprises a filling insulation portion extending between the trench and the buried conductive wiring.
20. The semiconductor device of claim 14 , wherein the dielectric liner is disposed on the bottom surface that exposes the portion of the substrate and on an inner side wall.