Erroneous bit discovery in memory system
Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.
1. A method, comprising:
monitoring, by a power management component, a power level associated with a memory system;
determining whether the power level varies from a range of power levels associated with the memory system; and
transmitting, to a controller, an indication that the power level varies from the range of power levels associated with the memory system to cause the controller to transfer information to a portion of a non-volatile memory.
2. The method of claim 1 , further comprising:
detecting that the power level associated with the memory system indicates a power loss at the memory system, wherein determining whether the power level varies from the range of power levels is based at least in part on detecting that the power level associated with the memory system indicates the power loss.
3. The method of claim 1 , further comprising:
determining that the power level decreases below a threshold, wherein determining whether the power level varies from the range of power levels associated with the memory system comprises is based at least in part on determining that the power level decreases below the threshold.
4. The method of claim 1 , further comprising:
detecting that the power level associated with the memory system is associated with a power change at the memory system, wherein determining whether the power level varies from the range of power levels is based at least in part on detecting that the power level associated with the memory system is associated with the power change.
5. The method of claim 1 , further comprising:
monitoring, by the power management component, a second power level associated with a system that includes the memory system;
determining whether the second power level varies from a second range of power levels associated with the system; and
transmitting, to the controller, a second indication that the second power level varies from the second range of power levels associated with the system.
6. The method of claim 5 , wherein the system comprises a host device associated with the memory system.
7. The method of claim 1 , wherein the power level is associated with a memory medium of the memory system.
8. An apparatus, comprising:
a memory system;
a power management component;
a controller; and
a circuit configured to cause the apparatus to:
monitor, via the power management component, a power level associated with the memory system;
determine whether the power level varies from a range of power levels associated with the memory system; and
transmit, to the controller, an indication that the power level varies from the range of power levels associated with the memory system to cause the controller to transfer information to a portion of a non-volatile memory.
9. The apparatus of claim 8 , wherein the circuit is further configured to cause the apparatus to:
detect that the power level associated with the memory system indicates a power loss at the memory system, wherein determining whether the power level varies from the range of power levels is based at least in part on detecting that the power level associated with the memory system indicates the power loss.
10. The apparatus of claim 8 , wherein the circuit is further configured to cause the apparatus to:
determine that the power level decreases below a threshold, wherein determining whether the power level varies from the range of power levels associated with the memory system comprises is based at least in part on determining that the power level decreases below the threshold.
11. The apparatus of claim 8 , wherein the circuit is further configured to cause the apparatus to:
detect that the power level associated with the memory system is associated with a power change at the memory system, wherein determining whether the power level varies from the range of power levels is based at least in part on detecting that the power level associated with the memory system is associated with the power change.
12. The apparatus of claim 8 , wherein the circuit is further configured to cause the apparatus to:
monitor, by the power management component, a second power level associated with a system that includes the memory system;
determine whether the second power level varies from a second range of power levels associated with the system; and
transmit, to the controller, a second indication that the second power level varies from the second range of power levels associated with the system.
13. The apparatus of claim 12 , wherein the system comprises a host device associated with the memory system.
14. The apparatus of claim 8 , wherein the power level is associated with a memory medium of the memory system.
15. A non-transitory computer-readable medium storing code comprising instructions, which when executed by a processor of an electronic device, cause the electronic device to:
monitor, by a power management component, a power level associated with a memory system;
determine whether the power level varies from a range of power levels associated with the memory system; and
transmit, to a controller, an indication that the power level varies from the range of power levels associated with the memory system to cause the controller to transfer information to a portion of a non-volatile memory.
16. The non-transitory computer-readable medium of claim 15 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
detect that the power level associated with the memory system indicates a power loss at the memory system, wherein determining whether the power level varies from the range of power levels is based at least in part on detecting that the power level associated with the memory system indicates the power loss.
17. The non-transitory computer-readable medium of claim 15 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
determine that the power level decreases below a threshold, wherein determining whether the power level varies from the range of power levels associated with the memory system comprises is based at least in part on determining that the power level decreases below the threshold.
18. The non-transitory computer-readable medium of claim 15 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
detect that the power level associated with the memory system is associated with a power change at the memory system, wherein determining whether the power level varies from the range of power levels is based at least in part on detecting that the power level associated with the memory system is associated with the power change.
19. The non-transitory computer-readable medium of claim 15 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
monitor, by the power management component, a second power level associated with a system that includes the memory system;
determine whether the second power level varies from a second range of power levels associated with the system; and
transmit, to the controller, a second indication that the second power level varies from the second range of power levels associated with the system.
20. The non-transitory computer-readable medium of claim 19 , wherein the system comprises a host device associated with the memory system.