IP Library Granted Patent US 11,698,806
Granted Patent B2
US 11,698,806 · App. 16/866,510 · Granted Jul 11, 2023

Hypercall acceleration for nested virtual machines

Inventors: Michael Tsirkin (Lexington, MA); Karen Noel (Pembroke, NH)
Assignee: Red Hat, Inc.
G06F9/45558G06F2009/45583
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Quick Facts
Patent No.
US 11,698,806
App. No.
16/866,510
Granted
Jul 11, 2023
Kind
B2
Abstract

Systems and methods for accelerating hypercalls for nested virtual machines. An example method may comprise executing, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine (VM). The Level 0 hypervisor receives a first function component from a Level 2 hypervisor managing a Level 3 VM, where the first function component performs a first functionality associated with a hypercall issued by the Level 3 VM; stores the first function component in a memory space associated with the Level 0 hypervisor; detects the hypercall issued by the Level 3 VM; and responsive to detecting the hypercall, executes the first function component to modify a VM context for the Level 3 VM.

Claims (61)

1. A method comprising:

executing, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine (VM);

receiving, by a Level 1 hypervisor managing a Level 2 VM, a first function component from a Level 2 hypervisor managing a Level 3 VM, wherein the first function component comprises a first set of instructions performing a first functionality associated with a hypercall issued by the Level 3 VM;

generating, by the Level 1 hypervisor, a second function component that performs a second functionality associated with the hypercall issued by the Level 2 VM, and wherein the second function component translates the first functionality to the second functionality;

chaining, by the Level 1 hypervisor, the first function component with the second function component to generate a chain of function components; and

providing the chain of function components to the Level 0 hypervisor to cause the Level 0 hypervisor to store the chain of function components in a memory space associated with the level 0 hypervisor.

2. The method of claim 1 , further comprising:

causing the Level 0 hypervisor to execute the first function component;

determining, by the Level 0 hypervisor, a completion status of the first function component; and

returning control to the Level 2 hypervisor in view of the completion status.

3. The method of claim 1 , further comprising:

causing the Level 0 hypervisor to execute the first function component;

determining, by the Level 0 hypervisor, a completion status of the first function component; and

executing, by the Level 0 hypervisor, the second function component in view of the completion status, the second function component to modify the second VM context.

4. The method of claim 3 , further comprising:

determining, by the Level 0 hypervisor, a second completion status of the second function component; and

returning control to the Level 2 hypervisor in view of the second completion status.

5. The method of claim 1 , wherein the first set of instructions performs a first modification of the first VM context.

6. The method of claim 5 , wherein the second functionality is implemented by a second set of instructions that translates the first modification of the first VM context into a second modification of the second VM context.

7. A system comprising:

a memory; and

a processing device, operatively coupled to the memory, the processing device to:

execute, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine (VM);

receive, by a Level 1 hypervisor managing a Level 2 VM, a first function component from a Level 2 hypervisor managing a Level 3 VM, wherein the first function component comprises a first set of instructions performing a first functionality associated with a hypercall issued by the Level 3 VM;

generate, by the Level 1 hypervisor, a second function component that performs a second functionality associated with the hypercall issued by the Level 2 VM, and wherein the second function component translates the first functionality to the second functionality;

chain, by the Level 1 hypervisor, the first function component with the second function component to generate a chain of function components; and

provide the chain of function components to the Level 0 hypervisor to cause the Level 0 hypervisor to store the chain of function components in a memory space associated with the level 0 hypervisor.

8. The system of claim 7 , wherein the processing device is further to:

receive, by the Level 2 hypervisor, instructions from the Level 3 VM pertaining to the first functionality;

validate, by the Level 2 hypervisor, the instructions from the Level 3 VM;

generate, by the Level 2 hypervisor, the first function component in view of the validated instructions; and

provide, by the Level 2 hypervisor, the first function component to the Level 1 hypervisor.

9. The system of claim 7 , wherein the processing device is further to:

receive, by the Level 1 hypervisor, instructions from the Level 2 VM pertaining to the second functionality;

validate, by the Level 1 hypervisor, the instructions from the Level 2 VM;

translate, by the Level 1 hypervisor, the instructions for the second functionality in view of the first functionality; and

generate, by the Level 1 hypervisor, the second function component in view of the validated instructions.

10. The system of claim 7 , wherein the processing device is further to:

determine that the first function component is a dependency of the second function component; and

configure the chain of function components in view of the dependency.

11. The system of claim 7 , wherein the processing device is further to:

determine that the first function component is not a dependency of the second function component; and

configure the chain of function components to indicate that the second function component is to be bypassed.

12. The system of claim 7 , wherein the processing device is further to:

responsive to detecting the hypercall issued by the Level 3 VM, causing the Level 0 hypervisor to execute one or more of the function components in the chain of function components.

13. A non-transitory computer readable storage medium comprising instructions, which when accessed by a processing device, cause the processing device to:

execute, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine (VM);

receive, by a Level 1 hypervisor managing a Level 2 VM, a first function component from a Level 2 hypervisor managing a Level 3 VM, wherein the first function component comprises a first set of instructions performing a first functionality associated with a hypercall issued by the Level 3 VM;

generate, by the Level 1 hypervisor, a second function component that performs a second functionality associated with the hypercall issued by the Level 2 VM, and wherein the second function component translates the first functionality to the second functionality;

chain, by the Level 1 hypervisor, the first function component with the second function component to generate a chain of function components; and

provide the chain of function components to the Level 0 hypervisor to cause the Level 0 hypervisor to store the chain of function components in a memory space associated with the level 0 hypervisor.

14. The non-transitory computer readable storage medium of claim 13 , wherein the processing device is further to:

cause the Level 0 hypervisor to execute the first function component;

determine, by the Level 0 hypervisor, a completion status of the first function component; and

return control to the Level 2 hypervisor in view of the completion status.

15. The non-transitory computer readable storage medium of claim 13 , wherein the processing device is further to: cause the Level 0 hypervisor to execute the first function component; determine, by the Level 0 hypervisor, a completion status of the first function component; and execute, by the Level 0 hypervisor, the second function component in view of the completion status, the second function component to modify a second VM context.

16. The non-transitory computer readable storage medium of claim 15 , wherein the processing device is further to:

determine, by the Level 0 hypervisor, a second completion status of the second function component; and

return control to the Level 2 hypervisor in view of the second completion status.

17. The non-transitory computer readable storage medium of claim 15 , wherein the first set of instructions performs a first modification of a first VM context.

18. The non-transitory computer readable storage medium of claim 17 , wherein the second functionality is implemented by a second set of instructions that translates the first modification of the first VM context into a second modification of the second VM context.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2020
From: TSIRKIN, MICHAEL; NOEL, KAREN
To: RED HAT, INC.
Reel/Frame 052566/0243 →
Continuity (1)
Related Publication 20210342176A1 · Nov 4, 2021