Memory chip or memory array for wide-voltage range in-memory computing using bitline technology
A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a pair of global read bitlines, a local group read port arranged between the pair of local bitlines and the pair of global read bitlines for selectively accessing one of the local bitlines depending on a state of a selected bitcell, and a local group precharge circuit operatively arranged between the pair of local bitlines.
1. A random-access memory comprising:
a memory array having a plurality of local memory groups, each local memory group including,
a plurality of bitcells arranged in a bitcell column;
a pair of local bitlines operatively connected to the plurality of bitcells;
a pair of global read bitlines;
a local group read port operatively arranged between the pair of local bitlines and the pair of global read bitlines for selectively accessing one of the local bitlines depending on a state of a selected bitcell;
a local group precharge circuit in operative connection with the pair of local bitlines; and
an in-memory computing logic including,
a global read bitlines multiplexer operatively connected to the pairs of global read bitlines of the plurality of local memory groups;
a bitline operational block operatively connected to an output of the global read bitlines multiplexer; and
an operation multiplexer operatively connected to an output of the bitline operational block.
2. The random-access memory of claim 1 ,
wherein the operation multiplexer includes a write back latch and a write back multiplexer.
3. The random-access memory of claim 1 , further comprising:
a word line driver operatively connected to word lines of the memory array;
two word line decoders operatively connected to inputs of the word line driver to provide for decoded addresses; and
a word line fusion circuit operatively connected to the decoded addresses.
4. The random-access memory of claim 3 , wherein the local group precharge circuit is configured to pre-charge the pair of local bitlines to VDD before activating a word line by the word line driver.
5. The random-access memory of claim 1 , further comprising:
a pair of amplifiers operatively connected to the pair of global read bitlines, respectively, for outputting data of the corresponding bitcells.
6. The random-access memory of claim 5 , further comprising:
an operational block for performing at least one of a logic, analog, and/or mathematical operation on signals of the outputs of the amplifiers.
7. The random-access memory of claim 6 , wherein the operational block includes a fast carry adder based on a dynamic Manchester Carry Chain adder operatively connected to outputs of the amplifiers.
8. The random-access memory of claim 7 , wherein the fast carry adder is precharged by the local group precharge circuit.
9. The random-access memory of claim 1 , wherein the memory array includes a first memory subarray and a second memory subarray, and a second pair of global read bitlines for accessing the second memory subarray.
10. The random-access memory of claim 1 , wherein the bitline operational block includes at least one of a logic circuit for performing a logic operation and a arithmetic operational circuit to perform an arithmetic operation.
11. A memory chip comprising:
a static random-access memory array having a plurality of local memory groups, each local memory group including,
a bitcell column including a plurality of bitcells;
a pair of local bitlines operatively connected to the plurality of bitcells;
a pair of global read bitlines;
a local group read port operatively arranged between the pair of local bitlines and the pair of global read bitlines for selectively accessing one of the local bitlines depending on a state of a selected bitcell;
a local group precharge circuit in operative connection with the pair of local bitlines; and
an in-memory computing logic including,
a global read bitlines multiplexer operatively connected to the pairs of global read bitlines of the plurality of local memory groups;
a bitline operational block operatively connected to an output of the global read bitlines multiplexer; and
an operation multiplexer operatively connected to an output of the bitline operational block.
12. The memory chip of claim 11 , wherein
the operation multiplexer includes a write back latch and a write back multiplexer.
13. The memory chip of claim 11 , further comprising:
a word line driver operatively connected to word lines of the memory array;
two-word line decoders operatively connected to inputs of the word line driver to provide for decoded addresses; and
a word line fusion circuit operatively connected to the decoded addresses.
14. The memory chip of claim 13 , wherein the local group precharge circuit is configured to pre-charge the pair of local bitlines to VDD before activating a word line by the word line driver.
15. The memory chip of claim 11 , further comprising:
a pair of amplifiers operatively connected to the pair of global read bitlines, respectively, for outputting data of the corresponding bitcells.
16. The memory chip of claim 15 , further comprising:
an operational block for performing at least one of a logic, analog, and/or mathematical operation on signals of the outputs of the amplifiers.
17. The memory chip of claim 16 , wherein the operational block includes a fast carry adder based on a dynamic Manchester Carry Chain adder operatively connected to outputs of the amplifiers.
18. The memory chip of claim 17 , wherein the fast carry adder is arranged in a buffered 4-bit configuration for sixteen (16) bitcell columns.
19. The memory chip of claim 17 , wherein the fast carry adder is precharged by the local group precharge circuit.
20. The memory chip of claim 11 , wherein the memory array includes a first memory subarray and a second memory subarray, and a second pair of global read bitlines for accessing the second memory subarray.
21. The memory chip of claim 11 , wherein the bitline operational block includes at least one of a logic circuit for performing a logic operation and a arithmetic operational circuit to perform an arithmetic operation.
22. A random-access memory comprising:
a memory array having a plurality of local memory groups, each local memory group including,
a plurality of bitcells arranged in a bitcell column;
a pair of local bitlines operatively connected to the plurality of bitcells;
a pair of global read bitlines;
a local group read port operatively arranged between the pair of local bitlines and the pair of global read bitlines for selectively accessing one of the local bitlines depending on a state of a selected bitcell;
a local group precharge circuit in operative connection with the pair of local bitlines;
a word line driver operatively connected to word lines of the memory array;
at least two word line decoders operatively connected to inputs of the word line driver to provide for at least two decoded addresses; and
a word line fusion circuit operatively connected to the decoded addresses.
23. A memory chip having the random-access memory of claim 22 .
24. The random access memory of claim 22 , wherein the word line fusion circuit is configured to translate the decoded addresses from the at least two word line decoders into a single address that combines the at least two decoded addresses, each one of the least two decoded addresses activating one of the word lines.