Transfer printing for RF applications
A semiconductor structure for RF applications comprises: a first μTP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.
1. A semiconductor structure for RF applications comprising:
a first μTP GaN transistor on an SOI wafer or die;
a first resistor connected to a gate of said first transistor; and
two or more stacked SOI transistors on said SOI wafer in series with said first μTP GaN transistor.
2. A semiconductor structure according to claim 1 , further comprising:
a second μTP GaN transistor on the SOI wafer or die; and
a second resistor connected to a gate of said second transistor.
3. A semiconductor structure according to claim 1 , further comprising:
an SOI transistor formed on said SOI wafer in series with said first μTP GaN transistor;
a second resistor connected to a gate of said SOI transistor; and
a third resistor connected a body of said SOI transistor.
4. A semiconductor structure according to claim 1 , further comprising:
a first switching branch comprising one or more μTP GaN transistors on the SOI wafer and connected to a first RF port;
a second switching branch comprising one or more μTP GaN transistors on the SOI wafer or die and connected to a second RF port, wherein each μTP GaN transistor in the first and second switching branch has a gate connected to a respective resistor.
5. A semiconductor structure according to claim 4 , wherein the first and second switching branches each comprises three μTP GaN transistors.
6. A semiconductor structure according to claim 4 , wherein each respective resistor is connected in parallel to a diode.
7. A semiconductor structure according to claim 4 , wherein said μTP GaN transistors in said first switching branch or said μTP GaN transistor in said second switching branch are on the same chiplet.
8. A semiconductor structure according to claim 4 , further comprising:
a switch driver formed on the SOI wafer and connected to said first and second switching branches;
a bias block connected to said switch driver.
9. A semiconductor structure according to claim 4 , wherein the first and second switching branches each comprises stacked SOI transistors connected in series with said one or more μTP GaN transistors.
10. A semiconductor structure according to claim 9 , further comprising a second switch driver and a second bias block formed on the SOI wafer for controlling said stacked SOI transistors.
11. A semiconductor structure according to claim 1 , wherein said structure is an SPDT switch.
12. A semiconductor structure according to claim 4 , further comprising one or more further switching branches, wherein the or each further switching branch comprises one or more μTP GaN transistors on the SOI wafer or die.
13. A semiconductor structure according to claim 12 , wherein said structure is an NPMT (N Poles and M Throws) switch.
14. A method of manufacturing a structure as claimed in claim 1 using a micro transfer printing process.