Systems and methods for fabrication of superconducting integrated circuits
Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
1. A method of fabricating a superconducting integrated circuit, the method comprising:
depositing a first dielectric layer;
depositing a negative photoresist mask over the first dielectric layer that traces out a negative pattern of a desired circuit pattern such that the desired circuit pattern corresponds to regions of the first dielectric layer that are not directly covered by the negative photoresist mask;
etching the desired circuit pattern into the first dielectric layer to produce open features in the first dielectric layer;
depositing a first superconducting metal layer over the first dielectric layer to at least partially fill the open features in the first dielectric layer;
planarizing the first superconducting metal layer;
depositing a second dielectric layer to produce a desired inner layer dielectric thickness, wherein the inner layer dielectric thickness is controlled by a deposition process; and
depositing a second superconducting metal layer above the second dielectric layer.
2. The method of claim 1 wherein the depositing a first superconducting metal layer includes depositing the first superconducting metal layer via electroplating.
3. The method of claim 1 wherein the planarizing the first superconducting metal layer includes planarizing the first superconducting metal layer by a chemical mechanical planarization.
4. The method of claim 1 wherein the depositing a first dielectric layer includes depositing the first dielectric layer to overlie a substrate.
5. The method of claim 4 wherein the depositing the first dielectric layer to overlie a substrate includes depositing the first dielectric layer to overlie a substrate, the substrate which includes at least one of silicon, silicon dioxide, or sapphire.
6. The method of claim 1 wherein the depositing a first dielectric layer includes depositing a layer of silicon dioxide.
7. The method of claim 1 further comprising depositing an etch-stop layer.
8. The method of claim 7 wherein the depositing an etch-stop layer includes depositing a layer of silicon nitride.
9. The method of claim 1 wherein the depositing a first superconducting metal layer includes depositing a superconducting metal layer that includes at least one of niobium or aluminum.
10. The method of claim 1 wherein the depositing a second dielectric layer includes depositing a dielectric layer having a second thickness, the second thickness greater than a first thickness of the first dielectric layer.
11. The method of claim 10 further comprising planarizing the second dielectric layer.
12. The method of claim 1 wherein the depositing a second superconducting metal layer includes depositing a superconducting metal layer that includes at least one of niobium or aluminum.