Catalyst influenced chemical etching for fabricating three-dimensional SRAM architectures
A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.
1. A three-dimensional (3D) SRAM device comprising:
two or more nanosheet FETs that are stacked vertically, along a vertical direction of a fin, on top of each other, wherein a wall angle of said fin is greater than 89.5 degrees, wherein said one or more nanosheet FETs are created using two or more layers of material different in at least one of the following: material, morphology, porosity, etch rates, thermal processing rates, doping concentration and dopant material; and
said one or more nanosheet FETs are separated by a material with a different composition than that of said fin or are separated by air.
2. The device as recited in claim 1 , wherein said fin comprises lateral layers of semiconducting materials with all around dielectric and gate metals.
3. The device as recited in claim 2 , wherein said lateral layers are made by etching alternating layers of silicon and silicon-germanium.
4. The device as recited in claim 3 , wherein said etching is performed by catalyst influenced chemical etching, wherein a catalyst of said catalyst influenced chemical etching comprises ruthenium.
5. The device as recited in claim 1 , wherein said wall angle is measured with respect to a critical feature dimension on top of said fin and at a bottom of said fin.
6. The device as recited in claim 1 , wherein a base of one of said one or more nanosheet FETs is surrounded by a dielectric for shallow trench isolation.
7. The device as recited in claim 1 , wherein at least one contact-node of a nanosheet FET of said one or more nanosheet FETs is contacted using a staircase contact.
8. A three-dimensional (3D) SRAM device comprising:
two or more fin field-effect transistors (FinFETs) that are stacked vertically, along a vertical direction of a fin, on top of each other, wherein a wall angle of said fin is greater than 89.5 degrees, wherein said one or more FinFETs are created using two or more layers of a material different in at least one of the following: material, morphology, porosity, etch rates, thermal processing rates, doping concentration and dopant material; and
said one or more FinFETs are separated by a material with a different composition than that of said fin or are separated by air.
9. The device as recited in claim 8 , wherein said fin comprises semiconducting material surrounded by dielectric and gate metals to form a transistor.
10. The device as recited in claim 8 , wherein said wall angle is measured with respect to a critical feature dimension on top of said fin and at a bottom of said fin.
11. The device as recited in claim 8 , wherein a base of one of said one or more FinFETs is surrounded by a dielectric for shallow trench isolation.
12. The device as recited in claim 8 , wherein at least one contact-node of a FinFET of said one or more FinFETs is contacted using a staircase contact.
13. The device as recited in claim 8 , wherein said fin comprises lateral layers of semiconducting materials with all around dielectric and gate metals, wherein said lateral layers are made by etching alternating layers of silicon and silicon-germanium, wherein said etching is performed by catalyst influenced chemical etching, wherein a catalyst of said catalyst influenced chemical etching comprises ruthenium.