IP Library Granted Patent US 11,561,845
Granted Patent B2
US 11,561,845 · App. 16/874,011 · Granted Jan 24, 2023

Memory access communications through message passing interface implemented in memory systems

Inventors: Samir Mittal (Palo Alto, CA); Gurpreet Anand (Pleasanton, CA); Anirban Ray (Santa Clara, CA); Parag R. Maharana (Dublin, CA)
Assignee: Micron Technology, Inc.
G06F9/546G06F9/544G06F12/0864G06F13/4221G06F15/17331G06N3/08G06F2212/6032
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Quick Facts
Patent No.
US 11,561,845
App. No.
16/874,011
Granted
Jan 24, 2023
Kind
B2
Abstract

A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.

Claims (43)

1. A memory system, comprising:

a bus communicatively coupled to a host system;

a peripheral device connected to the bus; and

a storage device connected to the bus, the storage device including a data orchestrator configured to:

implement a message passing interface with the peripheral device, the message passing interface bypassing the host system,

instruct a controller of the storage device to communicate directly with the peripheral device over the bus using the message passing interface in response to a current workload of the memory system by:

inputting the current workload into a predictive model, wherein the predictive model is trained to predict future use of data associated with the current workload,

receiving a prediction from the predictive model indicating that the data associated with the current workload will be accessed in the future, and

moving the data associated with the current workload to the peripheral device in response to the prediction, and

provide data access to the peripheral device through communications made using the message passing interface over the bus.

2. The memory system of claim 1 , wherein the data orchestrator communicates with the peripheral device without involving a host system connected to the bus.

3. The memory system of claim 2 , wherein the host system comprises a central processing unit (CPU).

4. The memory system of claim 1 , wherein the bus comprises a peripheral component interconnect express (PCIe) bus.

5. The memory system of claim 1 , wherein the peripheral device comprises a graphics processing unit (GPU).

6. The memory system of claim 1 , wherein the peripheral device comprises a controller of a second storage device coupled to the bus.

7. The memory system of claim 1 , wherein the peripheral device comprises a controller of a second storage device coupled to the bus through a computer network.

8. The memory system of claim 7 , wherein the bus is connected to the computer network via an InfiniBand (IB) interface.

9. The memory system of claim 1 , wherein the peripheral device comprises a second data orchestrator.

10. The memory system of claim 1 , wherein the peripheral device comprises a dynamic random access memory.

11. The memory system of claim 1 , wherein the data orchestrator performs predictive data movements using the message passing interface.

12. The memory system of claim 11 , wherein the predictive data movements are based on a logical volume configured in a virtual machine running on a host system.

13. The memory system of claim 12 , wherein a portion of the logical volume is in the storage device, and a portion of the logical volume is in the peripheral device.

14. The memory system of claim 12 , wherein the data orchestrator comprises a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) to implement an artificial neural network representing the predictive model.

15. The memory system of claim 14 , wherein the data orchestrator predicts the predictive data movements using the artificial neural network.

16. The memory system of claim 15 , wherein the data orchestrator trains the artificial neural network.

17. A method implemented in a system having a peripheral device and a storage device, the method comprising:

implementing a message passing interface;

communicating data from the storage device to the peripheral device using the message passing interface over a bus, wherein communicating data includes bypassing communication with a host system; and

providing data access to the peripheral device through communications made using the message passing interface over the bus, in response to a current workload by:

inputting the current workload into a predictive model, wherein the predictive model is trained to predict future use of data associated with the current workload,

receiving a prediction from the predictive model indicating that the data associated with the current workload will be accessed in the future, and

moving the data associated with the current workload to the peripheral device in response to the prediction.

18. The method of claim 17 , further comprising predicting a data movement over the bus prior to providing the data access.

19. A non-transitory computer storage medium storing instructions which, when executed by a system having a storage device and a peripheral device, cause the system to perform a method, the method comprising:

implementing a message passing interface;

communicating data from the storage device to the peripheral device using the message passing interface over a bus, wherein communicating data includes bypassing communication with a host system; and

providing data access to the peripheral device through communications made using the message passing interface over the bus in response to a current workload by:

inputting the current workload into a predictive model, wherein the predictive model is trained to predict future use of data associated with the current workload,

receiving a prediction from the predictive model indicating that the data associated with the current workload will be accessed in the future, and

moving the data associated with the current workload to the peripheral device in response to the prediction.

20. The non-transitory computer storage medium of claim 19 , wherein the peripheral device is a controller of a second storage device coupled to the bus through a computer network, and the method further comprises:

predicting data access to data in the second storage device configured as a portion of a logical volume in a virtual machine running in the host system; and

caching the data from the second storage device to the storage device via remote direct memory access.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2020
From: MITTAL, SAMIR; ANAND, GURPREET; RAY, ANIRBAN; MAHARANA, PARAG R.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 052664/0545 →
Continuity (3)
Continuation 16054890 · Aug 3, 2018
Provisional Application 62626419 · Feb 5, 2018
Related Publication 20200272530A1 · Aug 27, 2020