Memory-mapped two-dimensional error correction code for multi-bit error tolerance in DRAM

1. A method for providing error-correction protection associated with a storage device, the method comprising:

in response to a write request, organizing a block of data to be written to the storage device in a two-dimensional (2D) array;

forming a plurality of first-dimension sub-blocks by dividing the 2D array along a first dimension;

forming a plurality of second-dimension sub-blocks by dividing the 2D array along a second dimension;

in response to determining that second-dimension error correction code (ECC) encoding is enabled,

performing the second-dimension ECC encoding on the second-dimension sub-blocks to generate a set of second-dimension ECC bits; and

performing first-dimension ECC encoding on both the first-dimension sub-blocks and the generated set of second-dimension ECC bits to generate a first set of first-dimension ECC bits to protect the first-dimension sub-blocks and a second set of first-dimension ECC bits to protect the generated set of second-dimension ECC bits; and

writing the data block along with the second-dimension ECC bits and the first-dimension ECC bits to the storage device via a memory interface, wherein a data width of the memory interface equals to a length of a respective first-dimension sub-block plus a length of corresponding first-dimension ECC bits for the first-dimension sub-block, wherein the second-dimension ECC bits are treated as additional first-dimension sub-blocks to the data block and are similarly mapped to physical addresses in the storage device.

2. The method of claim 1 , wherein forming a respective second-dimension sub-block comprises concatenating a portion of data from a first first-dimension sub-block with a corresponding portion of data from an adjacent first-dimension sub-block.

3. The method of claim 1 , wherein the second-dimension ECC encoding is configured to provide a stronger error-correction protection than the first-dimension ECC encoding.

4. The method of claim 3 , wherein the block of data is 64-bytes long, wherein a respective first-dimension sub-block and a respective second-dimension sub-block are each 64-bits long, wherein performing the first-dimension ECC encoding comprises computing eight ECC bits for each first-dimension sub-block, and wherein performing the second-dimension ECC encoding comprises computing 16 ECC bits for each second-dimension sub-block.

5. The method of claim 3 , wherein the first-dimension ECC encoding is configured to provide single-bit error correction and double-bit error detection (SECDED), and wherein the second-dimension ECC encoding is configured to provide double-bit error correction and triple-bit error detection (DECTED).

6. The method of claim 1 , further comprising:

determining a physical address included in the write request;

determining whether the physical address is within a region of the storage device configured to be protected by the second-dimension ECC encoding by looking up an address-mapping table; and

in response to determining that the physical address is within a region of the storage device configured to be protected by the second-dimension ECC encoding, setting a second-dimension ECC encoding enable bit and calculating a second-dimension ECC address to which the second-dimension ECC bits are mapped.

7. The method of claim 6 , further comprising:

in response to determining that the physical address is not within a region of the storage device configured to be protected by the second-dimension ECC encoding, clearing the second-dimension ECC encoding enable bit.

8. The method of claim 1 , further comprising:

in response to a read request and determining that second-dimension ECC decoding is enabled, reading the data block along with the second-dimension ECC bits and the first-dimension ECC bits from the storage device; and

performing first-dimension ECC decoding for the data block and the second-dimension ECC bits based on the first-dimension ECC bits.

9. The method of claim 8 , further comprising:

in response to a read request and determining that the second-dimension ECC decoding is disabled, reading the data block along with the second-dimension ECC bits and the first-dimension ECC bits from the storage device;

performing first-dimension ECC decoding for the data block only based on corresponding ECC bits included in the first-dimension ECC bits; and

outputting the data block decoded using the first-dimension ECC decoding.

10. The method of claim 8 , further comprising:

in response to determining that the first-dimension ECC decoding corrects all errors in the data block, outputting the data block decoded using the first-dimension ECC decoding;

in response to determining that the first-dimension ECC decoding fails to correct all errors in the data block, performing second-dimension decoding for the data block based on the second-dimension ECC bits and outputting the data block decoded using the second-dimension ECC decoding.

11. A controller for facilitating error-correction protection associated with a storage device, further comprising:

a data serializer configured to serialize a block of cache line data to a two-dimensional (2D) array, wherein each row in the 2D array along a first dimension forms a first-dimension sub-block;

a data-arranging unit configured to form a plurality of second-dimension sub-blocks by dividing the 2D array along a second dimension;

a second-dimension error correction code (ECC) encoder configured to, in response to being enabled, perform second-dimension ECC encoding on the second-dimension sub-blocks to generate a set of second-dimension ECC bits;

a first-dimension ECC encoder configured to perform first-dimension ECC encoding on both first-dimension sub-blocks of the cache line data block and the generated set of second-dimension ECC bits to generate a first set of first-dimension ECC bits to protect the first-dimension sub-blocks and a second set of first-dimension ECC bits to protect the generated set of second-dimension ECC bits; and

a data-sending unit configured to send the data block along with the second-dimension ECC bits and the first-dimension ECC bits to the storage device via a memory interface, wherein a data width of the memory interface equals to a length of the first-dimension sub-block plus a length of corresponding first-dimension ECC bits for the first-dimension sub-block, wherein the second-dimension ECC bits are treated as additional first-dimension sub-blocks to the data block and are similarly mapped to physical addresses in the storage device.

12. The controller of claim 11 , wherein, while forming a respective second-dimension sub-block, the data-arranging unit is configured to concatenate a portion of data from a first first-dimension sub-block with a corresponding portion of data from an adjacent first-dimension sub-block.

13. The controller of claim 11 , wherein the second-dimension ECC encoder is configured to provide a stronger error-correction protection than the first-dimension ECC encoder.

14. The controller of claim 13 , wherein the block of cache line data is 64-bytes long, wherein a respective first-dimension sub-block and a respective second-dimension sub-block are each 64-bits long, wherein the first-dimension ECC encoder is configured to compute eight ECC bits for each first-dimension sub-block, and wherein the second-dimension ECC encoder is configured to compute 16 ECC bits for each second-dimension sub-block.

15. The controller of claim 13 , wherein the first-dimension ECC encoder is configured to provide single-bit error correction and double-bit error detection (SECDED), and wherein the second-dimension ECC encoder is configured to provide double-bit error correction and triple-bit error detection (DECTED).

16. The controller of claim 11 , further comprising an address controller configured to:

determine a physical address included in a write request associated with the cache line data block;

determine whether the physical address is within a region of the storage device configured to be protected by the second-dimension ECC encoding by looking up an address-mapping table; and

in response to determining that the physical address is within a region of the storage device configured to be protected by the second-dimension ECC encoding, set a second-dimension ECC encoding enable bit and calculate a second-dimension ECC address to which the second-dimension ECC bits are mapped.

17. The controller of claim 16 , wherein the address controller is further configured to:

in response to determining that the physical address is not within a region of the storage device configured to be protected by the second-dimension ECC encoding, clear the second-dimension ECC encoding enable bit.

18. The controller of claim 11 , further comprising a data-read module configured to read the data block along with the second-dimension ECC bits and the first-dimension ECC bits from the storage device in response to a read request and determining that second-dimension ECC decoding is enabled; and

a first-dimension ECC decoder configured to perform first-dimension ECC decoding for the data block and the second-dimension ECC bits based on the first-dimension ECC bits.

19. The controller of claim 18 , wherein the first-dimension ECC decoder is configured to:

in response to determining that the second-dimension ECC decoding is disabled, perform first-dimension ECC decoding for the data block only based on corresponding ECC bits included in the first-dimension ECC bits; and

send the data block decoded using the first-dimension ECC decoding to a cache coupled to the controller.

20. The controller of claim 18 , further comprising a second-dimension ECC decoder;

wherein the first-dimension ECC decoder is configured to output the data block decoded using the first-dimension ECC decoding to a cache coupled to the controller, in response to determining that the first-dimension ECC decoding corrects all errors in the data block;

wherein the first-dimension ECC decoder is configured to send the second-dimension ECC bits decoded using the first-dimension ECC decoding to the second-dimension ECC decoder to facilitate the second-dimension ECC decoder to perform second-dimension decoding for the data block, in response to determining that the first-dimension ECC decoding fails to correct all errors in the data block; and

wherein the second-dimension ECC decoder is configured to output the data block decoded using the second-dimension ECC decoding to the cache coupled to the controller.