Optical dielectric waveguide subassembly structures
An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
1. An optical subassembly comprising
a substrate;
an electrical interconnection layer disposed on the substrate, wherein the electrical interconnection layer comprises at least a first electrical interconnection line;
a waveguide formed on the interconnection layer, wherein the waveguide comprises a waveguide core, wherein the waveguide core comprises a patterned stack of adjacent and discrete SiON layers,
wherein the at least a first electrical interconnection line is configured to be electrically coupled to a first terminal of a first device disposed on the electrical interconnection layer.
2. An optical subassembly as in claim 1
wherein the first device is configured to optically communicate with the waveguide.
3. An optical subassembly as in claim 1
wherein each layer of the patterned stack of adjacent and discrete SiON layers is configured to have a stress having a magnitude less than or equal to 20 MPa.
4. An optical subassembly as in claim 1
wherein each layer of the patterned stack of adjacent and discrete SiON layers is configured to provide a waveguide having a stress having a magnitude less than or equal to 20 MPa.
5. An optical subassembly as in claim 1
wherein each layer of the patterned stack of adjacent and discrete SiON layers comprises a level of impurity, a level of homogeneity, or a level of uniformity to provide a waveguide having an optical loss less than or equal to 1 dB/cm.
6. An optical subassembly comprising
a substrate;
a first device fabricated on the substrate;
an electrical interconnection layer disposed on the substrate and on the device,
wherein the electrical interconnection layer comprises at least a first electrical interconnection line,
wherein the first electrical interconnection line is coupled to a first terminal of the first device;
a waveguide formed on the electrical interconnection layer, wherein the waveguide comprises a patterned stack of adjacent and discrete SiON layers.
7. An optical subassembly as in claim 6 further comprising
a second device formed on the electrical interconnection layer and comprising an optical element or an optoelectrical element aligned with the waveguide.
8. An optical subassembly as in claim 6 further comprising
a second device formed on the electrical interconnection layer and comprising an optical element aligned with the waveguide and an electrical element electrical connected with the first electrical interconnection line or a second electrical interconnection line in the electrical interconnection layer.
9. An optical subassembly as in claim 6 further comprising
a second device formed on the electrical interconnection layer and electrical connected with a second electrical interconnection line in the electrical interconnection layer.
10. An optical subassembly as in claim 6 further comprising
a second device formed on the electrical interconnection layer and electrical connected with the first electrical interconnection line for electrically communicate with the first device.
11. An optical subassembly as in claim 6
wherein each layer of the patterned stack of adjacent and discrete SiON layers is configured to have a stress having a magnitude less than or equal to 20 MPa.
12. An optical subassembly as in claim 6
wherein each layer of the patterned stack of adjacent and discrete SiON layers is configured to provide a waveguide having a stress having a magnitude less than or equal to 20 MPa.
13. An optical subassembly comprising
a substrate;
wherein a functionality of the substrate is susceptible to be degraded at temperatures greater than 400 C,
a waveguide formed on the substrate, wherein the waveguide comprises a patterned stack of adjacent and discrete SiON lavers,
wherein the waveguide is fabricated on the substrate at a temperature less than or equal to 400 C,
wherein the substrate comprises an electrical interconnection layer formed under the waveguide,
wherein the electrical interconnection layer comprises at least a first electrical interconnection line.
14. An optical subassembly as in claim 13
wherein the first electrical interconnection line is coupled to a first terminal of a first device formed on the electrical interconnection layer.
15. An optical subassembly as in claim 13
wherein the first electrical interconnection line is coupled to a first device formed on the electrical interconnection layer and aligned with the waveguide.
16. An optical subassembly as in claim 13
wherein the second electrical interconnection line is coupled to a second terminal of a second device formed under the electrical interconnection layer.
17. An optical subassembly as in claim 13
wherein each layer of the patterned stack of adjacent and discrete SiON layers comprises a stoichiometry of Si, O, and N to provide a waveguide having a stress having a magnitude less than or equal to 20 MPa.